Generating final mask pattern by performing inverse beam technology process

Patent metadata

Field	Value
Publication number	US-9747408-B2
Application number	US-201514832026-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	Aug 21, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes receiving an IC design layout; and performing an inverse beam technology (IBT) process to the IC design layout, thereby generating a final mask pattern, wherein the IBT process uses a single IBT model to simulate both a mask making process and a wafer making process.

First claim

What is claimed is:

1. An integrated circuit (IC) method comprising:
receiving an IC design layout;
performing an optical proximate correction (OPC) process to the IC design layout, thereby generating an OPCed mask pattern;
performing a mask proximate correction (MPC) process to the OPCed mask pattern, thereby generating an MPCed mask pattern;
fracturing the MPCed mask pattern;
identifying hot spots of the IC design layout according to the MPCed mask pattern; and
performing, using an apparatus, an inverse beam technology (IBT) process to the IC design layout in the hot spots, thereby generating a final mask pattern, wherein the IBT process uses a single IBT model to simulate both a mask making process and a wafer making process.

2. The method of claim 1 , wherein the IBT model is defined in a formula P(x, y)=Φ 3 (Φ 2 (Φ 1 (f(x, y)))), wherein
P(x, y) defines a simulated wafer contour;
f(x, y) defines an electron-beam shot map;
Φ 1 defines a mask making function that simulates the mask making process;
Φ 2 defines a wafer imaging function that simulates an imaging of the mask on the semiconductor wafer during the a lithography exposing process; and
Φ 3 defines a wafer pattern function that simulates characteristics of a photoresist coated on the semiconductor wafer.

3. The method of claim 2 , wherein the performing of the IBT process includes performing an iterative process to the IC design layout in the hot spots using a cost function defined as

min
f

⁢

{

∑
j

⁢



EPE
⁡

(

x
j

,

y
j

)



}

,

in which EPE is an edge placement error function.

4. The method of claim 2 , wherein the performing of the IBT process includes performing an iterative process to the IC design layout using a cost function defined a cost function with area difference as

min
f

⁢

{

∑
k

⁢



P
k

-

T
k



}

,

in which P k and T k represent the simulated wafer contour P(x, y) and the desired wafer target T in a k th region.

5. The method of claim 1 , further comprising generating an electron-beam shot map from the final mask pattern, wherein the electron-beam shot map to be used in an electron-beam lithography process to pattern a mask.

6. The method of claim 5 , further comprising performing the mask making process to the mask using the electron-beam shot map, wherein the mask making process includes the electron-beam lithography process.

7. The method of claim 6 , further comprising performing the wafer making process to a semiconductor wafer, wherein the wafer making process includes a lithography exposing process using the mask.

8. The method of claim 7 , wherein the cost function is further defined as

min
f

⁢

{

∑
k

⁢



P
k

-

T
k



}

,

in which P k and T k represent the simulated wafer contour P(x, y) and the desired wafer target T in a k th region.

9. The method of claim 1 , further comprising forming a final wafer pattern based on the IC design layout, wherein the final wafer pattern is a desired wafer pattern to be formed on a semiconductor wafer.

10. An integrated circuit (IC) method comprising:
performing an optical proximate correction (OPC) process to an IC design layout, thereby generating an OPCed mask pattern;
performing a mask proximate correction (MPC) process to the OPCed mask pattern, thereby generating an MPCed mask pattern;
identifying hot spots of the IC design layout according to the MPCed mask pattern; and
performing, using an apparatus, an inverse beam technology (IBT) process to the IC design layout in the hot spots, thereby generating a final mask pattern, wherein the IBT process uses an IBT model to simulate both a mask making process and a wafer making process.

11. The method of claim 10 , further comprising fracturing the MPCed mask pattern, and
wherein identifying hot spots of the IC design layout according to the MPCed mask pattern includes identifying hot spots of the IC design layout according to the fractured MPCed mask pattern.

12. The method of claim 10 , further comprising performing a verification process to the MPCed mask pattern, wherein the verification process includes running a mask rule check against a portion of the MPCed mask pattern.

13. The method of claim 12 , further comprising modifying the portion of the MPCed mask pattern when the portion fails the mask rule check.

14. The method of claim 10 , wherein performing, using the apparatus, the IBT process to the IC design layout in the hot spots includes performing the IBT process to the IC design layout only in the spots.

15. The method of claim 10 , wherein performing the OPC process to the IC design layout includes moving edges of a main feature and adding assist features t

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Hsu-Ting
• Liu Ru-Gun
• Chou Shuo-Yen
• Gau Tsai-Sheng

Classifications

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G03F7/705

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title

• G03F7/70433

  Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors · CPC title

• G03F7/70441

  Optical proximity correction [OPC] · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title