Sub-resolution assist feature implementation using shot optimization

Patent metadata

Field	Value
Publication number	US-9170481-B2
Application number	US-201414213813-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 14, 2013
Publication date	Oct 27, 2015
Grant date	Oct 27, 2015

Abstract

A design layout for a semiconductor chip includes information on shapes desired to be fabricated. Clusters of photolithographic exposure “shots” are generated and subject to a measure of shot density to approximate a mask shape that generates the desired fabricated shapes when exposed during wafer fabrication. A simulation is run on the clusters of shots to estimate the resulting fabrication shapes that the clusters of shots create. The clusters of shots are modified to align the estimated fabrication shapes more closely with desired fabrication shapes. The process of simulating and modifying the shots is iterative, repeating until the estimated fabrication shapes are within a desired error difference of the planned fabrication shape.

First claim

What is claimed is:

1. A computer-implemented method for shape analysis comprising:
determining a desired fabricated shape based on a semiconductor chip design layout corresponding to a physical chip, wherein the desired fabricated shape corresponds to the semiconductor design layout;
evaluating the semiconductor design layout to determine mask shapes, wherein the mask shapes include an assist feature which is determined comprising:
analyzing the semiconductor design layout to evaluate desired fabricated shapes using the assist feature to aid in fabrication of the desired fabricated shapes;
selecting a glyph that approximates the assist feature; and placing the glyph within the mask shapes;
establishing a shot density for shots used to generate mask shapes;
approximating, using one or more processors, mask shapes using shots based on the shot density;
estimating a resulting fabricated semiconductor layout based on the shots;
modifying the shots to make the resulting fabricated semiconductor layout to be closer to the desired fabricated shape; and
storing information on the shots onto computer storage media.

2. The computer-implemented method of claim 1 further comprising generating a semiconductor mask with the mask shapes based on the assist feature.

3. The computer-implemented method of claim 2 wherein the generating of the semiconductor mask is based on the shot density for the shots.

4. The computer-implemented method of claim 1 wherein the mask shapes include an assist feature which does not appear on a physical chip based on the semiconductor design layout.

5. The computer-implemented method of claim 1 wherein the mask shapes include an assist feature which is not in the semiconductor design layout.

6. The computer-implemented method of claim 1 further comprising obtaining a library of pre-determined shot clusters representing a plurality of assist shapes for the mask shapes.

7. The computer-implemented method of claim 6 further comprising selecting, from the library, an assist shape from the plurality of assist shapes where the assist shape is based on the desired fabricated shape.

8. The computer-implemented method of claim 1 wherein pre-determined shot clusters that comprise one or more mask shapes comprise glyphs.

9. The computer-implemented method of claim 1 further comprising controlling a variably shaped beam based on the shots.

10. The computer-implemented method of claim 1 further comprising determining a fixed-cost optimal quality of result (QOR) solution for the shots.

11. The computer-implemented method of claim 1 further comprising determining a required minimum shot configuration for the shots.

12. The computer-implemented method of claim 1 wherein the shots are created while bypassing polygon shape generation.

13. The computer-implemented method of claim 1 further comprising correcting the shots to eliminate harmful artifacts.

14. The computer-implemented method of claim 13 further comprising modifying patterns for the shots at boundaries between adjacent glyphs.

15. The computer-implemented method of claim 1 further comprising using a rule table to determine placement of shot clusters comprised of the shots.

16. The computer-implemented method of claim 1 further comprising characterizing the shots to generate pre-determined shot clusters.

17. The computer-implemented method of claim 16 further comprising storing the pre-determined shot clusters into a library.

18. The computer-implemented method of claim 1 wherein the approximating includes bypassing a polygon as an intermediate representation of the mask shapes.

19. A computer system for shape analysis comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors are configured to:
determine a desired fabricated shape based on a semiconductor chip design layout corresponding to the physical chip, wherein the desired fabricated shape corresponds to the semiconductor design layout;
evaluate the semiconductor design layout to determine mask shapes, wherein the mask shapes include an assist feature which is determined comprising:
analyzing the semiconductor design layout to evaluate desired fabricated shapes using the assist feature to aid in fabrication of the desired fabricated shapes;
selecting a glyph that approximates the assist feature; and placing the glyph within the mask shapes;
establish a shot density for the shots used to generate the mask shapes;
approximate, using the one or more processors, mask shapes using shots based on the shot density;
estimate a resulting fabricated semiconductor layout based on the shots;
modify the shots to make the resulting fabricated semiconductor layout to be closer to the desired fabricated shape; and
storing information on the shots onto computer storage media.

20. A computer program product embodied in a non-transitory computer readable medium for shape analysis comprising:
code for determining a desired fabricated shape based on a semiconductor chip design layout corresponding to the physical chip, wherein the desired fabricated shape corresponds to the semiconductor design layout;
code for evaluating the semiconductor design layout to determine mask shapes, wherein the mask shapes include an assist feature which is determined comprising:
analyzing the semiconductor design layout to evaluate desired fabricated shapes using the assist feature to aid in fabrication of the desired fabricated shapes;
selecting a glyph that approximates the assist feature; and placing the glyph within the mask shapes;
code for establishing a shot density for the shots used to generate the mask shapes;
code for approximating, using one or more processors, the mask shapes using shots based on the shot density;
code for estimating a resulting fabricated semiconductor layout based on the shots;
code for modifying the shots to make the resulting fabricated semiconductor layout to be closer to the desired fabricated shape; and
code for storing information on the shots onto computer storage media.

21. The computer program product of claim 20 wherein the mask shapes include an assist feature which does not appear on a physical chip based on the semiconductor design layout.

22. The computer program product of claim 20 further comprising obtaining a library of pre-determined shot clusters representing a plurality of assist shapes for the mask shapes.

23. The computer-implemented method of claim 18 wherein the approximating allows shot configurations to overlap.

24. The computer-implemented method of claim 23 wherein the approximating increases degrees of freedom for determining a minimum shot configuration.

25. The system of claim 19 wherein the mask shapes include an assist feature which does not appear on a physical chip based on the semiconductor design layout.

Assignees

• Synopsys Inc

Inventors

• Rieger Michael Lawrence
• Cecil Thomas Christopher
• Painter Benjamin David

Classifications

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G03F1/36 Primary

  Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title