Error monitoring of a memory device containing embedded error correction

Patent metadata

Field	Value
Publication number	US-9747148-B2
Application number	US-201715401744-A
Country	US
Kind code	B2
Filing date	Jan 9, 2017
Priority date	Feb 2, 2015
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

First claim

What is claimed is:

1. A dynamic random-access memory (DRAM) device having embedded error-correcting code (ECC), the DRAM device comprising:
a DRAM array;
a first register to store an error count;
a first register bank to store a set of error addresses;
an ECC controller, wherein the ECC controller is configured to perform error detection using an ECC, increment the error count whenever an error is detected, and write an error address in an available register in the first register bank;
a second register bank to store a plurality of decision parameters; and
a failure detection unit to predict failure of the DRAM device and to detect failing rows or columns of the DRAM device.

2. The DRAM device of claim 1 , further comprising a second register to store a multi-bit error count.

3. The DRAM device of claim 1 , further comprising a second register to store an uncorrectable error flag.

4. The DRAM device of claim 1 , further comprising a second register bank to store a set of bank-specific error counts, wherein each of the set of bank-specific error counts corresponds to a unique memory bank within the DRAM array.

5. A method for logging and correcting dynamic random-access memory (DRAM) errors, the method comprising:
detecting an error in a word in a DRAM device using an error-correcting code;
incrementing, in response to detecting the error, an error count stored in a first register;
saving, in response to detecting the error, an error address corresponding to a location of the error in an available register in a first register bank;
determining whether the error count exceeds a threshold; and
setting, in response to the error count exceeding the threshold, an error flag.

6. The method of claim 5 , further comprising:
determining whether the error is in a first memory bank; and
incrementing, in response to the error being detected in the first memory bank, a first bank-specific error count, wherein the first bank-specific error count stores a number of errors in the first memory bank and is stored in a second register bank.

7. The method of claim 5 , further comprising:
determining whether the error is uncorrectable; and
setting, in response to the error being uncorrectable, an uncorrectable error flag.

8. The method of claim 5 , further comprising executing, in response to the error flag being set, a repair action.

9. The method of claim 5 , the method further comprising:
determining a first error count at a first time;
determining a second error count at a second time, the second time being subsequent to the first time;
determining a number of new errors by comparing the second error count to the first error count;
determining whether the number of new errors is greater than a new error threshold; and
scheduling, in response to determining that the number of new errors exceeds the new error threshold, a repair action.

Assignees

• IBM

Inventors

• Healy Michael B
• Hunter Hillery C
• Kilmer Charles A
• Kim Kyu-Hyoun
• Maule Warren E

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/0766 Primary

  Error or fault reporting or storing · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title