Detecting a cryogenic attack on a memory device with embedded error correction

Patent metadata

Field	Value
Publication number	US-2016239663-A1
Application number	US-201514621506-A
Country	US
Kind code	A1
Filing date	Feb 13, 2015
Priority date	Feb 13, 2015
Publication date	Aug 18, 2016
Grant date	—

Abstract

Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

First claim

What is claimed is:

1 . A method for detecting and responding to a cryogenic attack on a dynamic random-access memory (DRAM) device, the method comprising:
receiving a set of memory information about a DRAM device; processing, using a set of decision parameters, the set of memory information to determine a set of error indicators; determining whether the set of error indicators match an attack syndrome; and disabling, in response to determining that the set of error indicators match the attack syndrome, access to the DRAM device.

2 . The method of claim 1 , wherein the set of error indicators comprises an error count.

3 . The method of claim 1 , wherein the set of error indicators comprises an error rate.

4 . The method of claim 1 , wherein the set of error indicators comprises an error acceleration.

5 . The method of claim 1 , wherein the set of error indicators comprises a number of sequential read operations without a write operation.

6 . The method of claim 1 , wherein the set of error indicators comprises a temperature of the DRAM device.

7 . The method of claim 1 , wherein:
the set of error indicators comprises an error rate and an error acceleration; and determining whether the set of error indicators match an attack syndrome comprises comparing the error rate to a first threshold and comparing the error acceleration to a second threshold.

8 . The method of claim 1 , wherein the disabling access to the DRAM device comprises tripping a fuse on the DRAM device.

9 . The method of claim 1 , wherein the disabling access to the DRAM device comprises writing a DRAM array to a known state.

10 . The method of claim 1 , wherein the attack syndrome is configurable by a user.

11 . A computer program product for detecting and responding to a cryogenic attack on a dynamic random-access memory (DRAM) device, the computer program product comprising:
one or more computer readable storage media and program instructions stored on at least one of the one or more computer readable storage media, the program instructions comprising:
program instructions to receive a set of memory information about a DRAM device;
program instructions to process, using a set of decision parameters, the set of memory information to determine a set of error indicators;
program instructions to determine whether the set of error indicators match an attack syndrome; and
program instructions to disable, in response to determining that the set of error indicators match the attack syndrome, access to the DRAM device.

12 . A system comprising:
a memory; and dynamic random-access memory (DRAM) control logic, wherein the DRAM control logic causes the memory to:
receive a set of memory information about a DRAM device;
process, using a set of decision parameters, the set of memory information to determine a set of error indicators;
determine whether the set of error indicators match an attack syndrome; and
disable, in response to determining that the set of error indicators match the attack syndrome, access to the DRAM device.

Assignees

• IBM

Inventors

• Healy Michael B
• Hunter Hillery C
• Kilmer Charles A
• Kim Kyu-Hyoun
• Maule Warren E

Classifications

• G11C11/40

  using transistors · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F21/554 Primary

  involving event detection and direct action · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title