Division circuit and microprocessor

Patent metadata

Field	Value
Publication number	US-9747074-B2
Application number	US-201414477282-A
Country	US
Kind code	B2
Filing date	Sep 4, 2014
Priority date	Feb 25, 2014
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

In an embodiment, a division circuit has an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor, a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when the overflow determination circuit determines that the division result overflows, and a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

First claim

What is claimed is:

1. A division circuit comprising:
an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor;
a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when it is determined that the division result will overflow; and
a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

2. The division circuit according to claim 1 , further comprising a sign determination circuit configured to determine a sign of a quotient obtained as a result of the division from the dividend and the divisor, wherein the replacement circuit changes the first value according to the result of the determination of the sign of the quotient made by the sign determination circuit.

3. The division circuit according to claim 1 , wherein the replacement circuit has:
a first selection circuit configured to select and output one of the dividend and the first value according to the result of the determination made by the overflow determination circuit; and
a second selection circuit configured to select and output one of the divisor and the second value according to the result of the determination made by the overflow determination circuit,
wherein selection and output of the first value and selection and output of the second value respectively performed by the first selection circuit and the second selection circuit enable stepwise division using the first value as the dividend and using the second value as the divisor.

4. The division circuit according to claim 1 , wherein the first value is stored in a first storage device, and the second value is stored in a second storage device.

5. The division circuit according to claim 4 , wherein each of the first storage device and the second storage device is rewritable.

6. The division circuit according to claim 4 , wherein the first storage device is capable of storing a plurality of the first values; the second storage device is capable of storing a plurality of the second values; and the replacement circuit replaces the dividend with a selected value out of the plurality of the first values and replaces the divisor with a selected value out of the plurality of the second values.

7. The division circuit according to claim 1 , further comprising a zero determination circuit configured to determine whether or not the divisor is zero, wherein the replacement circuit replaces the dividend with the first value and replaces the divisor with the second value when the zero determination circuit determines that the divisor is zero.

8. The division circuit according to claim 1 , wherein the first value and the second value are stored or overwritten in a register file.

9. A microprocessor comprising:
an instruction decoder configured to decode a division instruction; and
an arithmetic logic unit capable of executing stepwise division corresponding to the division instruction, the arithmetic logic unit having:
an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor;
a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when it is determined that the division result will overflow; and
a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

10. The microprocessor according to claim 9 , wherein the stepwise division circuit is an adder/subtractor.

11. The microprocessor according to claim 9 , wherein the arithmetic logic unit has a sign determination circuit configured to determine a sign of a quotient obtained as a result of the division from the dividend and the divisor, and wherein the replacement circuit changes the first value according to the result of the determination of the sign of the quotient made by the sign determination circuit.

12. The microprocessor according to claim 9 , wherein the replacement circuit has:
a first selection circuit configured to select and output one of the dividend and the first value according to the result of the determination made by the overflow determination circuit; and
a second selection circuit configured to select and output one of the divisor and the second value according to the result of the determination made by the overflow determination circuit,
wherein selection and output of the first value and selection and output of the second value respectively performed by the first selection circuit and the second selection circuit enable stepwise division using the first value as the dividend and using the second value as the divisor.

13. The microprocessor according to claim 9 , wherein the first value is stored in a first storage device, and the second value is stored in a second storage device.

14. The microprocessor according to claim 9 , wherein each of the first storage device and the second storage device is rewritable.

15. The microprocessor according to claim 9 , wherein the first storage device is capable of storing a plurality of the first values; the second storage device is capable of storing a plurality of the second values; and the replacement circuit replaces the dividend with a selected value out of the plurality of the first values and replaces the divisor with a selected value out of the plurality of the second values.

16. The microprocessor according to claim 9 , wherein the arithmetic logic unit further has a zero determination circuit configured to determine whether or not the divisor is zero, and wherein the replacement circuit replaces the dividend with the first value and replaces the divisor with the second value when the zero determination circuit determines that the divisor is zero.

17. The microprocessor according to claim 9 , wherein the first value and the second value are stored or overwritten in a register file.

Assignees

• Toshiba Kk

Inventors

• Sano Toru

Classifications

• G06F7/535

  Dividing only · CPC title

• G06F7/4991 Primary

  Overflow or underflow · CPC title

• G06F7/49921

  Saturation, i.e. clipping the result to a minimum or maximum value · CPC title