Wiring board with stacked embedded capacitors and method of making

Patent metadata

Field	Value
Publication number	US-9743526-B1
Application number	US-201615040564-A
Country	US
Kind code	B1
Filing date	Feb 10, 2016
Priority date	Feb 10, 2016
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A method of making a wiring board includes forming a first capacitor carrier layer with a first embedded chip capacitor, a first insulation layer disposed on an upper surface, a second insulation layer disposed on a lower surface, first upper and lower conductive vias in conductive contact with a first electrode, and second upper and lower conductive vias in conductive contact with a second electrode. The method also includes forming a second capacitor carrier layer similar to the first. The method further includes forming a bonded laminate comprising in sequence an upper insulation layer, the first capacitor carrier layer, a center insulation layer, the second capacitor carrier layer, and a lower insulation layer. The method also includes forming a through-hole through the laminate and forming a conductive coating within the through-hole to provide a conductive through-hole. A wiring board also includes the bonded laminate and the embedded capacitors.

First claim

What is claimed is:

1. A wiring board, comprising:
a bonded laminate, the bonded laminate comprising:
a first capacitor carrier layer having a first chip capacitor embedded therein;
a second capacitor carrier layer having a second chip capacitor embedded therein;
an upper insulation layer disposed on an upper surface of a first insulation layer of the first capacitor carrier layer;
a center insulation layer disposed on a lower surface of a second insulation layer of the first capacitor carrier layer, the center insulation layer including cured polymer, the second capacitor carrier layer disposed on a lower surface of the center insulation layer; and
a lower insulation layer disposed on a lower surface of a second insulation layer of the second capacitor carrier layer.

2. The wiring board of claim 1 , wherein:
the first capacitor carrier layer comprises: a first core substrate having an upper surface, a lower surface, and a first opening portion, the first chip capacitor embedded in the first opening portion having a first electrode and a second electrode, the first insulation layer disposed on the upper surface, the second insulation layer disposed on the lower surface, a first upper conductive via in conductive contact with the first electrode and extending through the first insulation layer, a second upper conductive via in conductive contact with the second electrode and extending through the first insulation layer, a first lower conductive via in conductive contact with the first electrode and extending through the second insulation layer, a second lower conductive via in conductive contact with the second electrode and extending through the second insulation layer; and
the second capacitor carrier layer comprises: a second core substrate having an upper surface, a lower surface, and a second opening portion, the second chip capacitor embedded in the second opening portion having a first electrode and a second electrode, a first insulation layer disposed on the upper surface, the second insulation layer disposed on the lower surface, a first upper conductive via in conductive contact with the first electrode and extending through the first insulation layer, a second upper conductive via in conductive contact with the second electrode and extending through the first insulation layer, a first lower conductive via in conductive contact with the first electrode and extending through the second insulation layer, a second lower conductive via in conductive contact with the second electrode and extending through the second insulation layer.

3. The wiring board of claim 1 , further comprising at least one conductive through-hole that extends through the bonded laminate to an outer surface of the upper insulation layer and an outer surface of the lower insulation layer.

4. The wiring board of claim 3 , wherein the conductive through-hole comprises a conductive coating formed on a through-hole bore, an insulator disposed on the conductive coating and filling the bore, and a pair of opposing conductive caps disposed on outer surfaces of the upper insulation layer and the lower insulation layer that are conductively connected to the conductive coating.

5. The wiring board of claim 3 , wherein the at least one conductive through-hole comprises a plurality of conductive through-holes.

6. The wiring board of claim 1 , wherein the first chip capacitor comprises a plurality of first chip capacitors embedded in a plurality of spaced apart first opening portions and the second chip capacitor comprises a plurality of second chip capacitors embedded in a plurality of spaced apart second opening portions.

7. The wiring board of claim 1 , wherein:
the wiring board comprises a microprocessor bonding portion, and wherein the plurality of first chip capacitors and the plurality of second chip capacitors are embedded within the wiring board under the microprocessor bonding portion; and
a total number of the first chip capacitors and the second chip capacitors is 12-48.

8. The wiring board of claim 1 , wherein the wiring board has a thickness of about 800 to about 1200 μm.

9. The wiring board of claim 1 , wherein each of the upper insulation layer and the lower insulation layer includes cured polymer.

10. A method of making a wiring board, comprising:
forming a first capacitor carrier layer having a first chip capacitor embedded therein;
forming a second capacitor carrier layer having a second chip capacitor embedded therein;
forming a bonded laminate comprising an upper insulation layer disposed on an upper surface of a first insulation layer of the first capacitor carrier layer, a center insulation layer disposed on a lower surface of a second insulation layer of the first capacitor carrier layer, the center insulation layer including cured polymer, the second capacitor carrier layer disposed on a lower surface of the center insulation layer, and a lower insulation layer disposed on a lower surface of a second insulation layer of the second capacitor carrier layer;
forming a through-hole that extends through the bonded laminate to an outer surface of the upper insulation layer and an outer surface of the lower insulation layer; and
forming a conductive coating within the through-hole to provide a conductive through-hole.

11. The method of claim 10 , wherein:
the first capacitor carrier layer comprises: a first core substrate having an upper surface, a lower surface, and a first opening portion, the first chip capacitor embedded in the first opening portion having a first electrode and a second electrode, the first insulation layer disposed on the upper surface, the second insulation layer disposed on the lower surface, a first upper conductive via in conductive contact with the first electrode and extending through the first insulation layer, a second upper conductive via in conductive contact with the second electrode and extending through the first insulation layer, a first lower conductive via in conductive contact with the first electrode and extending through the second insulation layer, a second lower conductive via in conductive contact with the second electrode and extending through the second insulation layer; and
the second capacitor carrier layer comprises: a second core substrate having an upper surface, a lower surface, and a second opening portion, the second chip capacitor embedded in the second opening portion having a first electrode and a second electrode, a first insulation layer disposed on the upper surface, the second insulation layer disposed on the lower surface, a first upper conductive via in conductive contact with the first electrode and extending through the first insulation layer, a second upper conductive via in conductive contact with the second electrode and extending through the first insulation layer, a first lower conductive via in conductive contact with the first electrode and extending through the second insulation layer, a second lower conductive via in conductive contact with the second electrode and extending through the second insulation layer.

12. The method of claim 11 , wherein the first upper conductive via, the second upper conductive via, the first lower conductive via, and the second lower conductive via of the first capacitor carrier layer are configured for independent electrical connection to respective independent electrical conductors of the first capacitor carrier layer and the first upper conductive via, the second upper conductive via, the first lower conductive via, and the second lower conductive via of the second capacitor carrier layer are configured for independent electrical connection to respective independent electrical conduc

Assignees

• IBM
• Shinko Electric Ind Co
• Shinko Electric Ind Co

Inventors

• Blackshear Edmund
• Hirabayashi Keiichi
• Miyazawa Yoichi
• Quinlan Brian W
• Sato Junji

Classifications

• H05K1/0298

  Multilayer circuits · CPC title

• H05K2201/0959

  Plated through-holes or plated blind vias filled with insulating material · CPC title

• H05K2201/10522

  Adjacent components · CPC title

• H05K1/185 Primary

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title