Substrate embedding passive element

Patent metadata

Field	Value
Publication number	US-9420683-B2
Application number	US-201314143727-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Dec 31, 2012
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A substrate embedding a passive element includes a first conductor pattern layer disposed on a lower surface thereof and a second conductor pattern layer disposed on an upper surface thereof; a first via electrically connecting between the passive element and the first conductor pattern layer; and a second via electrically connecting between the passive element and the second conductor pattern layer, in which a volume of the first via is larger than that of the second via.

First claim

What is claimed is:

1. A substrate embedding a passive element, comprising:
a first insulating layer in which a passive element having an external electrode is embedded;
a second insulating layer formed on an upper surface of the first insulating layer;
a third insulating layer formed on a lower surface of the first insulating layer;
a first conductor pattern layer disposed on a lower surface of the third insulating layer; a second conductor pattern layer disposed on an upper surface of the second insulating layer;
a third conductive pattern layer formed on the lower surface of the first insulating layer;
a fourth conductive pattern layer formed on the upper surface of the first insulating layer;
a first via electrically connecting between a lower surface of the external electrode and the first conductor pattern layer;
a second via electrically connecting between an upper surface of the external electrode and the second conductor pattern layer;
a third via penetrating the third insulating layer and electrically connecting between the third conductive pattern layer and the first conductive pattern layer;
a fourth via penetrating the first insulating layer and electrically connecting between the third conductive pattern layer and the fourth conductive pattern layer; and
a fifth via penetrating the second insulating layer and electrical connecting between the fourth conductive pattern layer and the second conductive pattern layer,
wherein the first via and the third via are both in contact with a conductive pattern of the first conductive pattern layer,
wherein the third via and the fourth via are both in contact with a conductive pattern of the third conductive pattern layer, and
wherein the fourth via and the fifth via are both in contact with a conductive pattern of the fourth conductive pattern layer.

2. The substrate embedding a passive element according to claim 1 , wherein a height of the first via is about 0.5 to 1.5 times as large as that of the second via.

3. The substrate embedding a passive element according to claim 2 , wherein a cross sectional area of a surface on which the first via contacts the lower surface of the external electrode is larger than that of a surface on which the second via contacts the upper surface of the external electrode.

4. The substrate embedding a passive element according to claim 2 , wherein a cross sectional area of a surface on which the first via contacts the second conductor pattern layer is larger than that of a surface on which the second via contacts the first conductor pattern layer.

5. The substrate embedding a passive element according to claim 2 , wherein among the first and second vias, the first via is disposed in plural, and the number of first vias is larger than the number of second vias.

6. The substrate embedding a passive element according to claim 1 , wherein the passive element is a multi-layered ceramic capacitor.

7. The substrate embedding a passive element according to claim 1 , wherein the passive element is longitudinally disposed between the first via and the second via along an axis orthogonal to the top surface of the first insulating layer.

8. The substrate embedding a passive element according to claim 1 , wherein a top surface of the passive element directly contacts a bottom surface of the second via and a bottom surface of the passive element directly contacts a top surface of the first via, and an axis extending from a top surface of the first via to a lower surface of the first via is disposed to a side of an axis extending from a top surface of the second via to a lower surface of the second via.

Assignees

• Samsung Electro Mech

Inventors

• Lee Doo Hwan
• Chung Yul Kyo
• Shin Yee Na
• Lee Seung Eun

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H01L23/49827

  Electricity · mapped topic