Bump structures, semiconductor device and semiconductor device package having the same

Patent metadata

Field	Value
Publication number	US-9741675-B2
Application number	US-201514599366-A
Country	US
Kind code	B2
Filing date	Jan 16, 2015
Priority date	Jan 16, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes a body, at least one conductive metal pad and at least one metal pillar. The body includes a first surface. The at least one conductive metal pad is disposed on the first surface. Each metal pillar is formed on a corresponding conductive metal pad. Each metal pillar has a concave side wall and a convex side wall opposite the first concave side wall, and the concave side wall and the convex side wall are orthogonal to the corresponding conductive metal pad.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a body comprising a first surface;
at least one conductive metal pad disposed on the first surface; and
at least one metal pillar, wherein each metal pillar is formed on a corresponding one of the at least one conductive metal pad and comprises a concave side wall and a convex side wall opposite the concave side wall, a center of curvature of the concave side wall coinciding with a center of curvature of the convex side wall, the concave side wall and the convex side wall being orthogonal to the corresponding conductive metal pad, wherein each metal pillar further comprises a first end wall and a second end wall, each of the first end wall and the second end wall connects the concave side wall and the convex side wall, the first end wall and the second end wall being orthogonal to the corresponding conductive metal pad.

2. The semiconductor device of claim 1 , wherein the first end wall is a convex wall comprising a first radius of curvature, and the second end wall is a convex wall comprising a second radius of curvature.

3. The semiconductor device of claim 2 , wherein the first radius of curvature is substantially the same as the second radius of curvature.

4. The semiconductor device of claim 1 , wherein the shape of the concave side wall represents an arc of a first circle, and the shape of the convex side wall represents an arc of a second circle different from the first circle.

5. The semiconductor device of claim 1 , wherein the first surface of the body has a rectangular shape, and the at least one metal pillar is disposed close to a corner of the first surface.

6. The semiconductor device of claim 5 , wherein the at least one metal pillar is disposed on a diagonal of the first surface.

7. The semiconductor device of claim 1 , wherein the at least one metal pillar is oriented such that the concave side wall is closer to a center of the first surface than is the convex side wall.

8. The semiconductor device of claim 7 , wherein the center of curvature of the concave side wall of the at least one metal pillar falls on a diagonal of the first surface.

9. The semiconductor device of claim 7 , wherein the center of curvature of the convex side wall of the least one metal pillar falls on a diagonal of the first surface.

10. A metal bump structure, comprising:
at least one metal pillar; and
a solder layer;
wherein an outer boundary of the metal bump structure comprises a first curve and a second curve opposite the first curve, wherein a center of curvature of the first curve and a center of curvature of the second curve coincide and fall on a same side of the at least one metal bump structure, wherein the outer boundary of the metal bump structure further comprises a first curved end and a second curved end, and each of the first curved end and the second curved end connects the first curve and the second curve.

11. The metal bump structure of claim 10 , wherein the first curved end is convex and comprises a first radius of curvature and the second curved end is convex and comprises a second radius of curvature.

12. A semiconductor device package, comprising:
a semiconductor device comprising an active surface;
a package substrate comprising a top surface; and
at least one metal bump structure connected between the active surface of the semiconductor device and the top surface of the package substrate, each metal bump structure comprising a concave side wall and a convex side wall opposite the concave side wall, the shape of the concave side wall representing an arc of a first circle, the shape of the convex side wall representing an arc of a second circle different from the first circle, the concave side wall and the convex side wall being orthogonal to the active surface, wherein each metal bump structure further comprises a first end wall and a second end wall, each of the first end wall and the second end wall connects the concave side wall and the convex side wall, the first end wall and the second end wall being orthogonal to the active surface.

13. A semiconductor device package, comprising:
a semiconductor device comprising an active surface;
a package substrate comprising a top surface; and
at least one metal bump structure connected between the active surface of the semiconductor device and the top surface of the package substrate, an outer boundary of each metal bump structure comprising a first curve and a second curve opposite the first curve, wherein a center of curvature of the first curve and a center of curvature of the second curve fall on a same side of the at least one metal bump structure, wherein the outer boundary of each metal bump structure further comprises a first curved end and a second curved end, and each of the first curved end and the second curved end connects the first curve and the second curve, wherein the center of curvature of the first curve and the center of curvature of the second curve of the at least one metal bump structure fall on a line extending through a center of the top surface.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen Dao-Long
• Yang Ping-Feng
• Lee Chang-Chi
• Chen Chien-Fan

Classifications

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title