Method of making metal substrates with structures formed therein
US-2024404922-A1 · Dec 5, 2024 · US
Bumpless build-up layer package including an integrated heat spreader
US9153552B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9153552-B2 |
| Application number | US-201414570785-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 15, 2014 |
| Priority date | Sep 28, 2012 |
| Publication date | Oct 6, 2015 |
| Grant date | Oct 6, 2015 |
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Abstract
Official abstract text for this publication.
An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a microelectronic die package, comprising: stacking a lower die surface of a microelectronic die onto a heat spreader in thermal communication with the heat spreader; forming a cavity through the heat spreader, wherein the cavity forms a direct interface with a portion of the lower die surface of the microelectronic die; forming an encapsulation material around the microelectronic die and the heat spreader; building up a plurality o…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9153552B2 cover?
- An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader sur…
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W40/228. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).