Method for producing optoelectronic semiconductor components, leadframe assembly and optoelectronic semiconductor component

Patent metadata

Field	Value
Publication number	US-9741616-B2
Application number	US-201314405393-A
Country	US
Kind code	B2
Filing date	May 3, 2013
Priority date	Jun 5, 2012
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

In one embodiment, the method is configured for producing optoelectronic semiconductor components ( 1 ) and includes the steps of:
providing a leadframe assembly ( 20 ) with a multiplicity of leadframes ( 2 ), each having at least two leadframe parts ( 21, 22 ); forming at least a part of the leadframe assembly ( 20 ) with a housing material for housing bodies ( 4 ); dividing the leadframe assembly ( 20 ) between at least one part of the columns (C) and/or the rows (R), wherein the leadframes ( 2 ) remain arranged in a matrix-like manner; equipping the leadframes ( 2 ) with at least one optoelectronic semiconductor chip ( 3 ); testing at least one part of the leadframes ( 2 ) equipped with the semiconductor chips ( 3 ) and formed with the housing material after the step of dividing; and separating to form the semiconductor components ( 1 ) after the step of forming and after the step of testing.

First claim

The invention claimed is:

1. A method for producing optoelectronic semiconductor components comprising the steps, in the following sequence, of:
providing a leadframe assembly with a multiplicity of leadframes arranged in rows and columns,
wherein each of the leadframes includes at least two leadframe parts which follow one another along the rows and each of the leadframes is provided for one of the optoelectronic semiconductor components,
wherein the leadframes and leadframe parts are interconnected by connecting webs so that the leadframe assembly is mechanically stabilized by the connecting webs,
wherein the leadframe assembly comprises at least one marginal row, the marginal row is the row located closest to an edge strip oriented in parallel therewith,
wherein in this marginal row, first leadframe parts of the marginal row are insulated from first leadframe parts of an adjacent row in the leadframe assembly so that there is no direct electrical connection between these adjacent first leadframe parts by a connecting web and so that there is only an indirect electrical connection via the edge strip,
wherein the connecting webs between the marginal row and the associated adjacent row are formed differently from the connecting webs between adjacent rows, none of which adjoins the marginal row, and
wherein the leadframe parts of adjacent rows which are not marginal rows are directly connected with each other along the columns by the connecting webs;
forming housing bodies of the optoelectronic semiconductor components by forming at least a part of the leadframe assembly with a housing material;
dividing the leadframe assembly exclusively along and between the marginal row and the associated edge strip, the respective connecting webs being cut through thereby, so that only the leadframes in the marginal row can individually be addressed,
wherein the leadframes remain arranged in a matrix-like manner;
equipping each of the leadframes with at least one optoelectronic semiconductor chip on the first leadframe parts;
testing at least one part of the leadframes equipped with the optoelectronic semiconductor chips and formed with the housing material; and
separating to form the optoelectronic semiconductor components,
wherein during the step of testing only one part of the equipped leadframes and the optoelectronic semiconductor chips mounted in the marginal row is tested to render a test result, a statistical evaluation takes place on the basis of the testing of this part of the leadframes and optoelectronic semiconductor chips and the statistical evaluation and the test result are used to make a decision regarding further processing of the leadframe assembly.

2. The method according to claim 1 , wherein dividing takes place between precisely two marginal rows and precisely two adjacent edge strips extending in parallel therewith, and
wherein the two marginal rows include between 10% and 40% of the leadframes inclusive.

3. The method according to claim 1 , wherein the step of testing the equipped leadframes and the optoelectronic semiconductor chips is performed along the rows individually.

4. A method for producing optoelectronic semiconductor components comprising the steps, in the following sequence, of:
providing a leadframe assembly with a multiplicity of leadframes arranged in rows and columns,
wherein each of the leadframes includes at least two leadframe parts which follow one another along the rows and each of the leadframes is provided for one of the optoelectronic semiconductor components, and
wherein the leadframes and leadframe parts are interconnected by connecting webs so that the leadframe assembly is mechanically stabilized by the connecting webs;
forming housing bodies of the optoelectronic semiconductor components by forming at least a part of the leadframe assembly with a housing material;
dividing the leadframe assembly along and between at least one part of at least the columns or the rows, the respective connecting webs being cut through thereby,
wherein the leadframes remain arranged in a matrix-like manner;
equipping the leadframes with at least one optoelectronic semiconductor chip;
testing at least one part of the leadframes equipped with the optoelectronic semiconductor chips and formed with the housing material; and
separating to form the optoelectronic semiconductor components after the step of forming and after the step of testing,
wherein the leadframe assembly includes at least one edge strip which is oriented in parallel with the rows,
wherein at least first leadframe parts in a marginal row on the edge strip are insulated from the first leadframe parts of the adjacent row in the leadframe assembly which is not yet divided,
wherein the first leadframe parts in the marginal row in the leadframe assembly which is not yet divided are electrically connected only to the edge strip, and
wherein during the step of dividing, the leadframe assembly is further continuously divided between the marginal row and the edge strip.

5. The method according to claim 4 , wherein during testing only one part of the equipped leadframes and the semiconductor chips mounted thereon is tested, and wherein a test result produced is statistically evaluated and based on this test result a decision is made regarding further processing of the leadframe assembly.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Schlereth Thomas
• Bestele Michael
• Gaertner Christian
• Gebuhr Tobias
• Gallmeier Hans-Christoph
• Holzer Peter
• Arndt Karlheinz
• Schneider Albert

Classifications

• H10P74/20

  characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/421

  Shapes or dispositions · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W70/438

  of side rails, e.g. having holes · CPC title