Metal reflow for middle of line contacts

Patent metadata

Field	Value
Publication number	US-9741577-B2
Application number	US-201514956720-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Dec 2, 2015
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first gate and a second gate arranged on a substrate;
a trench arranged between the first gate and the second gate, the trench extends from a surface of the first gate and a surface of the second gate to the substrate;
a liner disposed along sidewalls of the trench and a bottom portion of the trench in contact with the substrate;
a high purity cobalt disposed in the trench directly on the liner, the high purity cobalt completely filling the bottom portion of the trench and forming a thin film on upper sidewalls of the trench such that a thickness of the high purity cobalt on the upper sidewalls is substantially thinner than a thickness that completely fills the bottom portion of the trench, the high purity cobalt comprising less than 200 ppm impurities; and
a metal disposed directly on the high purity cobalt and filling remaining portions of the trench, the high purity cobalt and the metal forming a contact, the high purity cobalt being substantially free of voids, and the trench consisting essentially of the liner, the high purity cobalt, and the metal.

2. The semiconductor device of claim 1 , wherein the contact has an aspect ratio of at least 4.

3. The semiconductor device of claim 1 , wherein the liner is Co, Ti, CoTi, Ni, Pt, NiPt, NiPtTi, Ta, TaNi, TaAl, TaAlN, TiN, TiAl, TiAlN, or any combination thereof.

4. The semiconductor device of claim 1 , wherein the metal is copper, tungsten, aluminum, or a combination thereof.

5. The semiconductor device of claim 1 , wherein the contact has an aspect ratio in a range from about 3 to about 8.

Assignees

• IBM

Inventors

• Li Juntao
• Wang Junli
• Yang Chih-Chao

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10P14/44 Primary

  Physical vapour deposition [PVD] · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title