Display systems with compensation for line propagation delay

US9741279B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9741279-B2
Application numberUS-201615362541-A
CountryUS
Kind codeB2
Filing dateNov 28, 2016
Priority dateMay 23, 2012
Publication dateAug 22, 2017
Grant dateAug 22, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for characterizing and eliminating the effect of propagation delay on data and monitor lines of AMOLED panels is introduced. A similar technique may be utilized to cancel the effect of incomplete settling of select lines that control the write and read switches of pixels on a row.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of measuring a signal offset of signals on a signal line of a display system having a pixel circuit, the method comprising: generating a first signal from a first location on the signal line; measuring the first signal at a second location on the signal line upon expiry a first time duration sufficient to avoid settling effects, generating a first signal measurement; generating a second signal from the first location; measuring the second signal at the second location upon expiry of a second time duration insufficient to avoid settling effects, generating a second signal measurement; and comparing the first signal measurement with the second signal measurement to extract the signal offset. 2. The method of claim 1 , wherein the signal offset is a voltage signal offset, the signals are voltage signals, and the first and second signals are voltage signals. 3. The method of claim 1 , wherein the signal offset is a current signal offset, the signals are current signals, and the first and second signals are current signals. 4. The method of claim 1 , wherein the signal line is a data line connected to the pixel circuit at the second location, the signal offset is a programming signal offset, the signals are programming signals transmitted to the pixel circuit, and the first and second signals are programming signals. 5. The method of claim 4 , further comprising, prior to comparing the first signal measurement with the second signal measurement: extracting the first signal measurement from the second location over a monitor line after the expiry of the first time duration and after sufficient monitoring time to avoid settling effects on the monitor line; and extracting the second signal measurement from the second location over the monitor line after the expiry of the second time duration and after sufficient monitoring time to avoid settling effects on the monitor line, wherein measuring the first signal at the second location comprises storing a measured level of the first signal at the pixel circuit upon expiry of the first time duration and measuring the second signal at the second location comprises storing a measured level of the second signal at the pixel circuit upon expiry of the second time duration. 6. The method of claim 1 , wherein the signal line is a monitor line connected to the pixel circuit at the first location, the signal offset is a monitored signal offset, the signals are monitored signals received from the pixel circuit, and the first and second signals are monitored signals. 7. The method of claim 1 , wherein the extracting of the signal offset is carried out during an initial factory calibration and wherein the signal offset is used in subsequent operation of the display system. 8. The method of claim 1 , further comprising calibrating at least one of programming of the pixel circuit and monitoring of the pixel circuit with use of the extracted signal offset. 9. The method of claim 1 , wherein at least one of the first time duration and the second time duration vary as a function of a physical distance between the first location and the second location. 10. A display comprising: a pixel circuit; a driver for programming the pixel circuit; a monitor for monitoring the pixel circuit; a signal line connecting the pixel circuit with at least one of the driver and the monitor; and a controller configured to control the pixel circuit, and the at least one of the driver and the monitor to: generate a first signal from a first location on the signal line; measure the first signal at a second location on the signal line upon expiry a first time duration sufficient to avoid settling effects, generating a first signal measurement; generate a second signal from the first location; and measure the second signal at the second location upon expiry of a second time duration insufficient to avoid settling effects, generating a second signal measurement, the controller configured to compare the first signal measurement with the second signal measurement to extract a signal offset of signals on the signal line. 11. The display of claim 10 , wherein the signal offset is a voltage signal offset, the signals are voltage signals, and the first and second signals are voltage signals. 12. The display of claim 10 , wherein the signal offset is a current signal offset, the signals are current signals, and the first and second signals are current signals. 13. The display of claim 10 , wherein the signal line is a data line connected to the pixel circuit at the second location and connected to the driver at the first location, the signal offset is a programming signal offset, the signals are programming signals transmitted to the pixel circuit, and the first and second signals are programming signals. 14. The display of claim 13 , wherein the controller is further configured to control the monitor to, prior to the controller's comparing the first signal measurement with the second signal measurement: extract the first signal measurement from the second location over a monitor line after the expiry of the first time duration and after sufficient monitoring time to avoid settling effects on the monitor line; and extract the second signal measurement from the second location over the monitor line after the expiry of the second time duration and after sufficient monitoring time to avoid settling effects on the monitor line, and wherein the controller is further configured to control the pixel circuit to: perform said measuring of the first signal at the second location by storing a measured level of the first signal at the pixel circuit upon expiry of the first time duration; and perform said measuring of the second signal at the second location by storing a measured level of the second signal at the pixel circuit upon expiry of the second time duration. 15. The display of claim 10 , wherein the signal line is a monitor line connected to the pixel circuit at the first location an connected to the monitor at the second location, the signal offset is a monitored signal offset, the signals are monitored signals received from the pixel circuit, and the first and second signals are monitored signals. 16. The display of claim 10 , wherein the controller is configured to extract the signal offset during an initial factory calibration and is configured to use the signal offset in subsequent operation of the display system. 17. The display of claim 10 , wherein the controller is further configured to calibrate at least one of programming of the pixel circuit and monitoring of the pixel circuit with use of the extracted signal offset. 18. The display of claim 10 , wherein at least one of the first time duration and the second time duration vary as a function of a physical distance between the first location and the second location.

Assignees

Inventors

Classifications

  • using an active matrix · CPC title

  • G09G3/32Primary

    semiconductive, e.g. using light-emitting diodes [LED] · CPC title

  • Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

  • Calibration of display systems · CPC title

  • with pixel circuitry controlling the current through the light-emitting element · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9741279B2 cover?
A method for characterizing and eliminating the effect of propagation delay on data and monitor lines of AMOLED panels is introduced. A similar technique may be utilized to cancel the effect of incomplete settling of select lines that control the write and read switches of pixels on a row.
Who is the assignee on this patent?
Ignis Innovation Inc
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 22 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).