Method to controllably etch silicon recess for ultra shallow junctions

Patent metadata

Field	Value
Publication number	US-9735272-B2
Application number	US-201615070584-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	May 19, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method of forming a semiconductor device that includes forming a germanium including material on source and drain region portions of a silicon containing fin structure, and annealing to drive germanium into the source and drain region portions of the fin structure. The alloyed portions of fin structures composed of silicon and germanium are then removed using a selective etch. After the alloyed portions of the fin structures are removed, epitaxial source and drain regions are formed on the remaining portions of the fin structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate structure present on a channel portion of a fin structure, the fin structure having a first cross section for the channel portion and a second cross section for the source and drain region portions of the fin structure;
a spacer present on a sidewall of the gate structure, wherein a trench in the channel region portion of the fin structure extends beneath the spacer; and
epitaxial source and drain region structures are present on the source and drain region portions of the fin structure, wherein a portion of the epitaxial source and drain region structures extends into the trench underlying the spacer, the inside edge of the epitaxial source and drain region extending into the trench being aligned with a sidewall of the gate structure.

2. The semiconductor device of claim 1 , wherein the first cross section has a first width, and the second cross section has a second width, wherein the second width is less than the first width.

3. The semiconductor device of claim 1 , wherein the first cross section has a first width ranging from 6 nm to 10 nm.

4. The semiconductor device of claim 1 , wherein the second cross section has a second width ranging from 2 nm to 4 nm.

5. The semiconductor device of claim 1 wherein the fin structure is composed of a silicon including material.

6. The semiconductor device of claim 1 , wherein a silicon including material of the fin structure may be single crystal silicon, monocrystalline silicon, polycrystalline silicon, silicon doped with carbon (Si:C) and combinations thereof.

7. The semiconductor device of claim 1 , wherein the fin structure may have a height ranging from 5 nm to 200 nm.

8. The semiconductor device of claim 1 , wherein the epitaxial source regions and epitaxial drain regions comprises a material selected from the group consisting of silicon, silicon germanium, silicon doped with carbon, compound semiconductors, and combinations thereof.

9. The semiconductor device of claim 1 , wherein the epitaxial source regions and epitaxial drain regions are n-type or p-type doped.

10. The semiconductor device of claim 1 , wherein the spacer comprises a dielectric material.

11. The semiconductor device of claim 1 , wherein the spacer is in direct contact with a sidewall of the gate structure.

12. A semiconductor device comprising:
a gate structure present on a channel portion of a fin structure, the fin structure having a first cross section having a first width ranging from 6 nm to 10 nm for the channel portion and a second cross section having a second width ranging from 2 nm to 4 nm for the source and drain region portions of the fin structure;
a spacer present on a sidewall of the gate structure, wherein a trench in the channel region portion of the fin structure extends beneath the spacer; and
epitaxial source and drain region structures are present on the source and drain region portions of the fin structure, wherein a portion of the epitaxial source and drain region structures extends into the trench underlying the spacer, the inside edge of the epitaxial source and drain region extending into the trench being aligned with a sidewall of the gate structure.

13. The semiconductor device of claim 12 , wherein the fin structure is composed of a silicon including material.

14. The semiconductor device of claim 12 , wherein the silicon including material of the fin structure may be single crystal silicon, monocrystalline silicon, polycrystalline silicon, silicon doped with carbon (Si:C) and combinations thereof.

15. The semiconductor device of claim 12 , wherein the fin structure may have a height ranging from 5 nm to 200 nm.

16. The semiconductor device of claim 12 , wherein the epitaxial source regions and epitaxial drain regions comprises a material selected from the group consisting of silicon, silicon germanium, silicon doped with carbon, compound semiconductors, and combinations thereof.

17. The semiconductor device of claim 12 , wherein the epitaxial source regions and epitaxial drain regions are n-type or p-type doped.

18. The semiconductor device of claim 12 , wherein the spacer comprises silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), hafnium oxide (HfO 2 ), silicon carbides (SiCN), silicon carbonitrides, silsequioxanes, siloxanes, boron phosphate silicate glass (BPSG) or combinations thereof.

19. The semiconductor device of claim 12 , wherein the spacer has a width ranging from 2.0 nm to 15.0 nm.

20. The semiconductor device of claim 12 , wherein the spacer is in direct contact with a sidewall of a gate structure.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic

• H01L29/161

  Electricity · mapped topic

• H01L29/7851

  Electricity · mapped topic