Methods of forming gate structures for CMOS based integrated circuit products and the resulting devices

Patent metadata

Field	Value
Publication number	US-9024388-B2
Application number	US-201313919676-A
Country	US
Kind code	B2
Filing date	Jun 17, 2013
Priority date	Jun 17, 2013
Publication date	May 5, 2015
Grant date	May 5, 2015

Abstract

One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.

First claim

What is claimed is:

1. A method of forming replacement gate structures for an NMOS transistor and a PMOS transistor, comprising:
performing at least one etching process to remove a sacrificial gate structure for said NMOS transistor and a sacrificial gate structure for said PMOS transistor to thereby define an NMOS gate cavity and a PMOS gate cavity;
depositing a gate insulation layer in said NMOS gate cavity and in said PMOS gate cavity;
depositing a first metal layer on said gate insulation layer in said NMOS gate cavity and in said PMOS gate cavity;
performing at least one process operation to selectively form a metal-silicide material layer only on said first metal layer within said NMOS gate cavity but not on said first metal layer within said PMOS gate cavity; and
forming gate cap layers within said NMOS and PMOS gate cavities.

2. The method of claim 1 , wherein said metal-silicide material is a silicide of a refractory metal or a transition metal.

3. The method of claim 1 , wherein said metal-silicide material is tungsten silicide.

4. The method of claim 1 , wherein said gate insulation layer is a layer of high-k insulating material.

5. The method of claim 1 , wherein said first metal layer is comprised of titanium nitride.

6. The method of claim 1 , wherein performing said at least one process operation to selectively form said metal-silicide material layer only on said first metal layer within said NMOS gate cavity but not on said first metal layer within said PMOS gate cavity comprises:
depositing a silicon-containing material layer so as to over-fill said NMOS gate cavity and said PMOS gate cavity;
performing an etching process so as to recess an upper surface of said silicon-containing material layer and thereby result in a first portion of said silicon-containing material layer being positioned on said first metal layer within said NMOS gate cavity and a second portion of said silicon-containing material layer being positioned on said first metal layer within said PMOS gate cavity;
forming a masking layer that covers said NMOS gate cavity but leaves said PMOS gate cavity exposed;
with said masking layer in place, removing said second portion of said silicon-containing material layer within said PMOS gate cavity so as to thereby expose said first metal layer within said PMOS gate cavity;
removing said masking layer;
depositing a second metal layer on said first portion of said silicon-containing material layer positioned within said NMOS gate cavity and on said exposed first metal layer within said PMOS gate cavity;
converting at least a portion of said first portion of said silicon-containing material layer within said NMOS gate cavity into a metal silicide material that is positioned on said first metal layer in said NMOS gate cavity; and
forming gate cap layers within said NMOS and PMOS gate cavities.

7. A method of forming replacement gate structures for an NMOS transistor and a PMOS transistor, comprising:
performing at least one etching process to remove a sacrificial gate structure for said NMOS transistor and a sacrificial gate structure for said PMOS transistor to thereby define an NMOS gate cavity and a PMOS gate cavity;
depositing a gate insulation layer in said NMOS gate cavity and in said PMOS gate cavity;
depositing a first metal layer on said gate insulation layer in said NMOS gate cavity and in said PMOS gate cavity;
performing at least one first process operation to form a silicon-containing material layer on said first metal layer in said NMOS gate cavity and on said first metal layer within said PMOS gate cavity;
performing at least one second process operation to selectively remove said silicon-containing material layer from within said PMOS gate cavity while leaving said silicon-containing material layer positioned within said NMOS gate cavity and thereby expose said first metal layer within said PMOS gate cavity;
depositing a second metal layer on said silicon-containing material layer within said NMOS gate cavity and on said exposed first metal layer within said PMOS gate cavity;
converting at least a portion of said silicon-containing material layer within said NMOS gate cavity into a metal-silicide material that is positioned on said first metal layer in said NMOS gate cavity; and
forming gate cap layers within said NMOS and PMOS gate cavities.

8. The method of claim 7 , wherein said metal-silicide material is a silicide of a refractory metal or a transition metal.

9. The method of claim 7 , wherein said metal-silicide material is tungsten silicide.

10. The method of claim 7 , wherein said silicon-containing material is comprised of polysilicon or amorphous silicon.

11. The method of claim 7 , wherein said sacrificial gate structures are comprised of a silicon dioxide gate insulation layer and a polysilicon gate electrode positioned above said silicon dioxide gate insulation layer.

12. The method of claim 7 , wherein said first metal layer is titanium nitride, said silicon-containing material layer is comprised of polysilicon or amorphous silicon and said second metal layer is tungsten.

13. The method of claim 7 , wherein, after forming said metal-silicide material, a portion of said second metal layer remains positioned on said metal-silicide material within said NMOS cavity.

14. The method of claim 7 , wherein performing said at least one first process operation comprises:
depositing said silicon-containing material layer so as to over-fill said NMOS gate cavity and said PMOS gate cavity; and
performing an etching process so as to recess an upper surface of said silicon-containing material layer and thereby result in a first portion of said silicon-containing material layer being positioned on said first metal layer within said NMOS gate cavity and a second portion of said silicon-containing material layer being positioned on said first metal layer within said PMOS gate cavity.

15. The method of claim 14 , wherein performing said at least one second process operation comprises:
forming a masking layer that covers said NMOS gate cavity but leaves said PMOS gate cavity exposed; and
with said masking layer in place, removing said second portion of said silicon-containing material layer within said PMOS gate cavity so as to thereby expose said first metal layer within said PMOS gate cavity.

16. A method of forming replacement gate structures for an NMOS transistor and a PMOS transistor, comprising:
performing at least one etching process to remove a sacrificial gate structure for said NMOS transistor and a sacrificial gate structure for said PMOS transistor to thereby define an NMOS gate cavity and a PMOS gate cavity;
depositing a high-k gate insulation layer in said NMOS gate cavity and in said PMOS gate cavity;
depositing a first metal layer on said high-k gate insulation layer in said NMOS gate cavity and in said PMOS gate cavity;
depositing a silicon-containing material layer so as to over-fill said NMOS gate cavity and said PMOS gate cavity;
performing an etching process so as to recess an upper surface of said silicon-containing material layer and thereby result in a first portion of said silicon-containing material layer being positioned on said first metal layer within said NMOS gate cavity and a second portion of said silicon-containing material layer being positioned on said first metal layer within said PMOS gate cavity;
forming a masking layer that covers said NMOS gate cavity but leaves said PMOS gate cavity exposed;
with said masking layer in place, removing said second portion of said silicon-containing material

Assignees

• Globalfoundries Inc

Inventors

• Choi Kisik
• Xie Ruilong

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title