Method for incorporating stress sensitive chip scale components into reconstructed wafer based modules

Patent metadata

Field	Value
Publication number	US-9735128-B2
Application number	US-201414177974-A
Country	US
Kind code	B2
Filing date	Feb 11, 2014
Priority date	Feb 11, 2013
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Techniques for constructing an electronic module are provided herein. For example, the techniques include orienting at least one die having a top side (e.g., a first side), a bottom side (e.g., a second side) and one or more side walls, on a substrate with the top side of the die proximate the substrate, coating the bottom side and each of the side walls of the die with a stress buffer material, forming a reconstructed wafer by encapsulating the coated die within a mold compound, and removing the substrate to expose the top side of the die.

First claim

What is claimed is:

1. A method for constructing an electronic module, the method comprising the steps of:
orienting at least one primary die having a top side, a bottom side and one or more die side walls on a substrate with the top side of the die proximate the substrate;
forming a reconstructed wafer by encapsulating the primary die within a mold compound;
removing the substrate to expose the top side of the primary die and a top side of the reconstructed wafer, the top side of the primary die and the top side of the reconstructed wafer being substantially co-planar;
forming a cavity in the reconstructed wafer, the cavity having a bottom and defining one or more cavity side walls in the reconstructed wafer extending from the bottom of the cavity and terminating at the top side of the reconstructed wafer; and
disposing a secondary die having a front side, a bottom side and one or more side walls in the cavity such that the bottom side of the secondary die is proximate to the bottom of the cavity.

2. The method of claim 1 , further comprising:
attaching the bottom side of the secondary die to the bottom of the cavity using stress buffer material.

3. The method of claim 1 , wherein disposing the secondary die in the cavity further comprises disposing the secondary die in the cavity so as to leave space between the one or more side walls of the secondary die and the one or more cavity side walls defined by the cavity in the reconstructed wafer, the method further comprising:
filling the space with fill material such that the fill material terminates at the substantially co-planar top side of the primary die and the top side of the reconstructed wafer.

4. The method of claim 3 , wherein the fill material is a stress buffer material.

5. The method of claim 3 , wherein the fill material is epoxy based material.

6. The method of claim 1 , further comprising:
disposing a dielectric film on the top side of the reconstructed wafer and at least one of the top side of the primary die and the top side of the secondary die.

7. The method of claim 1 , further comprising:
disposing one or more metal layers on the top side of the primary die and the top side of the secondary die to form a front interconnect layer.

Assignees

• Charles Stark Draper Laboratory Inc

Inventors

• Karpman Maurice

Classifications

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/073

  of die-attach connectors · CPC title