Integrated circuit devices having through-silicon vias and methods of manufacturing such devices

Patent metadata

Field	Value
Publication number	US-9735090-B2
Application number	US-201514873453-A
Country	US
Kind code	B2
Filing date	Oct 2, 2015
Priority date	Oct 6, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a semiconductor structure;
a through-silicon-via (TSV) structure that extends in a first direction and that penetrates through the semiconductor structure;
a connection terminal on the semiconductor structure, the connection terminal including an upper surface that is electrically connected to the TSV structure, a bottom surface that is opposite the upper surface, and a side wall that extends between the bottom surface and the upper surface;
a metal capping layer that includes a flat capping portion that covers the bottom surface of the connection terminal, and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers the side wall of the connection terminal; and
a solder structure that surrounds the metal capping layer on the connection terminal,
wherein the solder structure extends to cover a portion of the side wall of the connection terminal that is not covered by the wedge-shaped capping portion, while surrounding the wedge-shaped capping portion.

2. The integrated circuit device of claim 1 , wherein the entirety of the metal capping layer is formed of the same material, and wherein the wedge-shaped capping portion has a thickness that decreases with increasing distance from the bottom surface of the connection terminal.

3. The integrated circuit device of claim 1 , wherein the flat capping portion of the metal capping layer has a thickness in the first direction of about 0.05 μm to about 0.5 μm.

4. The integrated circuit device of claim 1 , wherein the portion of the flat capping portion of the metal capping layer that contacts the bottom surface of the connection terminal has a thickness variation within ±3%.

5. The integrated circuit device of claim 1 , wherein the metal capping layer comprises a precious metal.

6. The integrated circuit device of claim 1 , wherein the connection terminal comprises a conductive pad, a solder ball, a solder bump, or a redistribution conductive layer.

7. The integrated circuit device of claim 1 , wherein the connection terminal comprises Ni, Cu, Al, or a combination thereof.

8. The integrated circuit device of claim 1 , further comprising a metal layer that comprises Ti, Cu, Ni, Au, NiV, NiP, TiNi, TiW, TaN, Al, Pd, CuCr, or a combination thereof between the TSV structure and the connection terminal.

9. The integrated circuit device of claim 1 , wherein the semiconductor structure comprises a substrate and an interlayer insulating layer that covers the substrate, and the TSV structure penetrates through the substrate but does not fully penetrate the interlayer insulating layer.

10. The integrated circuit device of claim 1 , wherein the semiconductor structure comprises a substrate, an interlayer insulating layer that covers the substrate, and an inter-metal insulating layer that covers the interlayer insulating layer, and the TSV structure penetrates through the substrate, the interlayer insulating layer, and the inter-metal insulating layer.

11. The integrated circuit device of claim 1 , wherein the wedge-shaped capping portion covers no more than half a length of the side wall of the connection terminal.

12. The integrated circuit device of claim 1 , wherein the side wall of the connection terminal extends upwardly at a right angle from the bottom surface of the connection terminal and meets the upper surface of the connection terminal at a right angle.

13. An integrated circuit device comprising:
a semiconductor structure;
a through-silicon-via (TSV) structure that extends in a first direction and that penetrates through the semiconductor structure;
a connection terminal on the semiconductor structure, the connection terminal including an upper surface that is electrically connected to the TSV structure, a bottom surface that is opposite the upper surface, and a side wall that extends between the bottom surface and the upper surface; and
a metal capping layer that includes a flat capping portion that covers the bottom surface of the connection terminal, and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers the side wall of the connection terminal,
wherein the side wall of the connection terminal has a first length, and a side of the wedge-shaped capping portion that partially covers the side wall of the connection terminal has a second length that is less than or equal to half the first length.

14. The integrated circuit device of claim 13 , wherein the second length is in a range of about 0.1 μm to about 3 μm.

15. The integrated circuit device of claim 13 , further comprising a solder ball that surrounds the wedge-shaped capping portion, wherein the solder ball directly contacts the side wall of the connection terminal.

16. An integrated circuit device comprising:
a semiconductor structure that includes a through-silicon-via (TSV) structure;
a connection terminal that is electrically connected to the TSV structure that has a bottom surface, an upper surface that is opposite the bottom surface, and a side wall that extends between the bottom surface and the upper surface; and
a metal capping layer that includes a flat capping portion that is on the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that extends onto the side wall of the connection terminal,
wherein the wedge-shaped capping portion covers no more than half the length of the side wall of the connection terminal.

17. The integrated circuit device of claim 16 , further comprising a metal layer between the TSV structure and the connection terminal.

18. The integrated circuit device of claim 17 , wherein the connection terminal is on a bottom surface of the metal layer and the metal capping layer is on a bottom surface of the connection terminal, and wherein the portion of the flat capping portion of the metal capping layer that contacts the bottom surface of the connection terminal has a thickness variation within ±3%.

19. The integrated circuit device of claim 16 , further comprising a solder ball that surrounds the wedge-shaped capping portion, wherein the solder ball directly contacts the side wall of the connection terminal.

20. The integrated circuit device of claim 16 , wherein the side wall of the connection terminal extends upwardly at a right angle from the bottom surface of the connection terminal and meets the upper surface of the connection terminal at a right angle.

Assignees

• Choi Ju-Il
• Fujisaki Atsushi
• Park Byung-Iyul
• Park Ji-Soon
• Jang Joo-Hee
• Jin Jeong-Gi
• Samsung Electronics Co Ltd

Inventors

• Choi Ju-Il
• Fujisaki Atsushi
• Park Byung-Iyul
• Park Ji-Soon
• Jang Joo-Hee
• Jin Jeong-Gi

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title