Stack packages including diffusion barriers over sidewalls of through via electrodes and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9257413-B2
Application number	US-201414189876-A
Country	US
Kind code	B2
Filing date	Feb 25, 2014
Priority date	Aug 29, 2013
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

First claim

What is claimed is:

1. A stack package comprising:
an upper chip over a lower chip;
a lower through via electrode substantially penetrating the lower chip and including a protrusion portion that protrudes from a backside surface of the lower chip;
a backside passivation layer covering the backside surface of the lower chip and exposing the protrusion portion;
a backside bump substantially coupled to the protrusion portion;
a front side bump electrically coupled to a chip contact portion of the upper chip and further coupled to the backside bump; and
a molding member exposing a backside surface of the upper chip and provided over sidewalls of the lower chip and sidewalls of the upper chip,
wherein the backside passivation layer comprises:
a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip; and

a second insulation layer provided over the first insulation layer.

2. The stack package of claim 1 , wherein the first insulation layer is a diffusion barrier.

3. The stack package of claim 1 , wherein the backside passivation layer further includes a third insulation layer provided over a surface of the second insulation layer.

4. The stack package of claim 1 , wherein the upper chip has a smaller size than the lower chip.

5. The stack package of claim 1 , wherein the upper chip has a greater size than the lower chip.

6. The stack package of claim 1 , further comprising:
an outer connection terminal disposed over a front side surface of the lower chip and extending over a bottom surface of the molding member; and
a redistribution line electrically coupling the outer connection terminal to the lower through via electrode and disposed over the front side surface of the lower chip.

7. The stack package of claim 1 , further comprising an intermediate chip between the lower chip and the upper chip,
wherein the intermediate chip comprises:
an intermediate front side bump electrically coupled to the lower chip;
an intermediate through via electrode penetrating the intermediate chip and including a protrusion portion that protrudes from a backside surface of the intermediate chip;
an intermediate backside passivation layer provided over the backside surface of the intermediate chip and exposing the protrusion portion of the intermediate through via electrode; and
an intermediate backside bump coupled to the protrusion portion of the intermediate through via electrode, and
wherein the intermediate backside passivation layer comprises:
a first intermediate insulation layer provided over a sidewall of the protrusion portion of the intermediate through via electrode and the backside surface of the intermediate chip; and
a second intermediate insulation layer provided over the first intermediate insulation layer.

8. The stack package of claim 2 , wherein the second insulation layer is an insulation buffer layer.

9. The stack package of claim 3 , wherein the third insulation layer is a diffusion barrier layer.

10. The stack package of claim 6 , wherein the redistribution line extends over the bottom surface of the molding member.

11. A stack package comprising:
an upper chip disposed over a lower chip that a lower through via electrode penetrates;
a molding member provided over sidewalls of the lower chip and sidewalls of the upper chip;
an outer connection terminal disposed over a front side surface of the lower chip and over a bottom surface of the molding member; and
a redistribution line electrically coupling the outer connection terminal to the lower through via electrode and disposed over the front side surface of the lower chip,
wherein the redistribution line extends directly onto the bottom surface of the molding member.

12. The stack package of claim 11 , further comprising:
a backside passivation layer provided over a backside surface of the lower chip and exposing a protrusion portion of the lower through via electrode, the protrusion portion protruding from the backside surface of the lower chip;
a backside bump substantially coupled to the protrusion portion; and
a front side bump electrically coupled to a chip contact portion of the upper chip and further coupled to the backside bump,
wherein the backside passivation layer comprises:
a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip; and
a second insulation layer provided over the first insulation layer.

13. The stack package of claim 11 , wherein the upper chip has a smaller size than the lower chip.

14. The stack package of claim 11 , wherein the upper chip has a greater size than the lower chip.

15. The stack package of claim 11 , wherein the molding member exposes a backside surface of the upper chip.

16. The stack package of claim 12 , wherein the backside passivation layer further includes a third insulation layer provided over a surface of the second insulation layer.

17. The stack package of claim 12 , wherein the backside passivation layer has a thickness substantially equal to a height of the protrusion portion.

Assignees

• Sk Hynix Inc

Inventors

• Yang Seung Taek
• Kim Jong Hoon
• Oh Tac Keun
• Na Song

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title