Method for forming semiconductor device structure with fine line pitch and fine end-to-end space

Patent metadata

Field	Value
Publication number	US-9735028-B2
Application number	US-201514789337-A
Country	US
Kind code	B2
Filing date	Jul 1, 2015
Priority date	Mar 12, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H 2 ). The method further includes controlling a flow rate of the hydrogen gas (H 2 ) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

First claim

What is claimed is:

1. A method for forming a semiconductor device structure, comprising:
receiving a substrate;
forming a bottom layer, a middle layer, and a top layer on the substrate;
patterning the top layer to form a patterned top layer;
performing a plasma process to the top layer to improve a line width roughness (LWR) of the top layer, wherein the plasma process comprises using a mixed gas comprising hydrogen gas (H 2 );
continuously performing the plasma process on the middle layer to pattern the middle layer, wherein the step of continuously performing the plasma process on the middle layer further comprises forming a protection layer on sidewalls of the middle layer; and
controlling a flow rate of the hydrogen gas (H 2 ) to improve an etching selectivity of the middle layer to the top layer, wherein the patterned middle layer comprises a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

2. The method for forming the semiconductor device structure as claimed in claim 1 , the middle layer has an etching selectivity relative to the top layer in a range from about 1.2 to about 100.

3. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the flow rate of the hydrogen gas (H 2 ) is in a range from 0.1 sccm to about 300 sccm.

4. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the mixed gas further comprises fluorine-containing gas, inert gas or combinations thereof.

5. A method for forming a semiconductor device structure, comprising:
receiving a substrate;
forming a dielectric layer on the substrate;
forming a hard mask layer on the dielectric layer;
forming a bottom layer, a middle layer, and a top layer on the hard mask layer;
patterning the top layer to form a patterned top layer;
patterning the middle layer by a patterning process comprising a plasma process to form a patterned middle layer, wherein the plasma process is performed by using a mixed gas comprising hydrogen gas (H 2 );
patterning the bottom layer to form a patterned bottom layer;
patterning the hard mask layer by using the patterned top layer, the patterned middle layer, and patterned bottom layer as a mask to form a patterned hard mask layer;
removing the patterned top layer, the patterned middle layer, and the patterned bottom layer;
forming a second bottom layer, a second middle layer, and a second top layer on the patterned hard mask layer;
patterning the second top layer to form a patterned second top layer; and
patterning the second middle layer by a second plasma process to form a patterned second middle layer, wherein the second middle layer is made of a silicon-containing compound, and the second plasma process comprises using a mixed gas comprising hydrogen gas (H 2 ).

6. The method for forming the semiconductor device structure as claimed in claim 5 , wherein the middle layer has an etching selectivity relative to the top layer in a range from about 1.2 to about 100.

7. The method for forming the semiconductor device structure as claimed in claim 5 , wherein a volume ratio of hydrogen gas (H 2 ) to the mixed gas is in a range from about 3 vol % to about 60 vol %.

8. The method for forming the semiconductor device structure as claimed in claim 5 , wherein the plasma process is used to improve a line width roughness (LWR) of the middle layer.

9. The method for forming the semiconductor device structure as claimed in claim 5 , wherein patterning the middle layer further comprises forming a protection layer on sidewalls of the middle layer.

10. The method for forming the semiconductor device structure as claimed in claim 5 , wherein a flow rate of hydrogen gas (H 2 ) in the plasma process is in a range from 0.1 sccm to about 300 sccm.

11. The method for forming the semiconductor device structure as claimed in claim 5 , the mixed gas further comprising fluorine-containing gas, inert gas or combinations thereof.

12. The method for forming the semiconductor device structure as claimed in claim 11 , wherein the fluorine-containing gas comprises nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), hexafluoroethane (C 2 F 6 ), tetrafluoromethane (CF 4 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), octofluoropropane (C 3 F 8 ), octofluorocyclobutane (C 4 F 8 ), octofluoroisobutylene (C 4 F 8 ) or fluorine (F 2 ).

13. A method for forming a semiconductor device structure, comprising:
receiving a substrate;
forming a dielectric layer on the substrate;
forming a hard mask layer on the dielectric layer;
forming a bottom layer, a middle layer, and a top layer on the hard mask layer, wherein the middle layer is made of a silicon-containing compound;
patterning the top layer to form a patterned top layer;
performing a plasma process to the top layer to improve a line width roughness (LWR) of the top layer, wherein the plasma process comprises using a mixed gas comprising hydrogen gas (H 2 );
continuously performing the plasma process on the middle layer to form a protection film on sidewalls of the top layer and sidewalls of the middle layer;
continuously performing the plasma process on the middle layer to remove a portion of the middle layer to form a patterned middle layer;
patterning the bottom layer to form a patterned bottom layer; and
patterning the hard mask layer by using the patterned top layer, the patterned middle layer, and the patterned bottom layer as a mask to form a patterned hard mask layer.

14. The method for forming the semiconductor device structure as claimed in claim 13 , wherein the middle layer has an etching selectivity relative to the top layer in a range from about 1.2 to about 100.

15. The method for forming the semiconductor device structure as claimed in claim 13 , wherein a flow rate of hydrogen gas (H 2 ) in the plasma process is in a range from 0.1 sccm to about 300 sccm.

16. The method for forming the semiconductor device structure as claimed in claim 13 , wherein a volume ratio of hydrogen gas (H 2 ) to the mixed gas is in a range from about 3 vol % to about 60 vol %.

17. The method for forming the semiconductor device structure as claimed in claim 13 , wherein the mixed gas further comprises fluorine-containing gas, inert gas, or combinations thereof.

18. The method for forming the semiconductor device structure as claimed in claim 13 , wherein the plasma process is performed at a pressure in a range from about 5 mT to about 20 mT.

19. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the LWR of the top layer is between about 2 nm and about 4 nm after performing the plasma process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Hung-Hao
• Chen Yu-Shu
• Liu Yu-Cheng

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/088

  involving partial etching of via holes · CPC title