Fast start up, ultra-low power bias generator for fast wake up oscillators

Patent metadata

Field	Value
Publication number	US-9733662-B2
Application number	US-201113192107-A
Country	US
Kind code	B2
Filing date	Jul 27, 2011
Priority date	Jul 27, 2011
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Various embodiments relate to a bias generator including: a bias generator circuit; a master startup circuit that applies current to a first node in the bias generator circuit; a second startup circuit that applies current to additional nodes in the bias generator circuit; and a power switch that receives a power from a power supply and that provides power to the bias generator circuit, the master startup circuit, and the second startup circuit.

First claim

We claim:

1. A bias generator comprising:
a bias generator circuit;
a master startup circuit that is configured to apply a first startup current to a first node in the bias generator circuit;
a second startup circuit that is configured to apply a second startup current to additional nodes in the bias generator circuit; and
a power switch that is configured to receive power from a power supply and provide power to the bias generator circuit, wherein the master startup circuit is configured to receive a first timing control signal, the second startup circuit is configured to receive a second timing control signal, the second timing control signal is a delayed version of the first timing control signal, the power switch, the master startup circuit, and the second startup circuit are turned on in a desired order, and both the first timing control and the second timing control signal are applied to the master startup circuit.

2. The bias generator of claim 1 , further comprising:
delay elements that are configured to receive an external timing control signal to produce the first and second timing control signals.

3. The bias generator of claim 1 , further comprising:
a power down circuit that is configured to power the bias generator down.

4. The bias generator of claim 1 , wherein the bias generator circuit further comprises:
a cascoded PMOS transistor pair; and
a cascoded NMOS transistor pair.

5. The bias generator of claim 4 , wherein the cascoded PMOS transistor pair is connected between a power supply line and the cascoded NMOS transistor pair, the cascoded NMOS transistor pair is connected between a ground and the cascoded PMOS transistor pair, and the master startup circuit is connected to a node in the cascoded NMOS transistor pair.

6. The bias generator of claim 1 , wherein the bias generator circuit is configured to bias an oscillator.

7. A method of producing a bias signal, comprising:
supplying power through a power switch from a power supply to a bias generator circuit;
applying, with a master startup circuit, a first startup current to a first node in the bias generator circuit;
applying, with a second startup circuit, a second startup current to additional nodes in the bias generator circuit; and
outputting the bias signal, wherein a first timing control signal controls the application of the first startup current, a second timing control signal controls the application of the second startup current, the second timing control signal is a delayed version of the first timing control signal, the power switch, the master startup circuit, and the second startup circuit are turned on in a desired order, and both the first timing control and the second timing control signal are applied to the master startup circuit.

8. A method of controlling a bias generator, comprising:
receiving an external timing control signal;
applying the external timing control signal to a master startup circuit;
producing a first timing control signal by delaying the external timing control signal;
applying the first timing control signal to the master startup circuit and a second startup circuit;
producing a second timing control signal by delaying the external timing control signal; and
applying the second timing control signal to a power switch to supply power to the bias generator.

9. The method of claim 8 , wherein producing the second timing control signal includes delaying the first timing control signal.

10. The method of claim 8 , further comprising:
applying a current signal from the master startup circuit to a node in the bias generator circuit.

11. The method of claim 10 , further comprising:
applying a current signal from the second startup circuit to additional nodes in the bias generator circuit.

12. The method of claim 11 , wherein the node is in a cascoded NMOS transistor pair in the bias generator circuit.

13. The method of claim 12 , wherein the additional nodes includes a first additional node, a second additional node, and a third additional node, the first additional node is at a gate of an upper transistor of the cascoded NMOS transistor pair, the second additional node is at a gate of an upper transistor of a cascoded PMOS transistor pair, and the third additional node is at a gate of a lower transistor of the cascoded PMOS transistor pair.

14. The method of claim 8 , further comprising:
producing a third timing control signal by delaying the external timing control signal; and
applying the third timing control signal to a power down circuit.

15. The method of claim 14 , further comprising:
applying the external timing control signal to a total power down circuit.

16. The method of claim 15 , wherein the total power down circuit connects and disconnects an output of the master startup circuit to a ground.

17. The bias generator of claim 1 , wherein the second timing control signal is applied to both the master startup circuit and the second startup circuit, and a third timing control signal is applied to the power switch.

18. The bias generator of claim 3 , wherein the power switch is configured to control leakage currents in a total power down mode.

Assignees

• Mahooti Kevin
• Gandhi Sanket
• Nxp Bv

Inventors

• Mahooti Kevin
• Gandhi Sanket

Classifications

• G05F1/10

  Regulating voltage or current  (G05F1/02 takes precedence) · CPC title

• G05F3/242 Primary

  with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage · CPC title

• H03L3/00

  Starting of generators · CPC title

• G05F3/26

  Current mirrors · CPC title