Automatic compilation method and framework for generating a layout of integrated memory-compute circuit
US-2024403527-A1 · Dec 5, 2024 · US
US9507897B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9507897-B2 |
| Application number | US-201414457357-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 12, 2014 |
| Priority date | Jun 14, 2014 |
| Publication date | Nov 29, 2016 |
| Grant date | Nov 29, 2016 |
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One or more circuit arrangements and techniques for modeling are provided. In some embodiments, a circuit arrangement includes at least one of a first current source, a second current source, a first diode, a second diode, and a switching component. In some embodiments, the switching component includes a bipolar junction transistor (BJT). In some embodiments, the circuit arrangement is integrated into a metal oxide semiconductor (MOS) device. When the circuit arrangement is integrated into a MOS device, at least one of a substrate current leakage, a junction breakdown, or a diode reverse recovery (DRR) effect is predictable for the MOS device.
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What is claimed: 1. A circuit arrangement comprising: a first current source having a first current input and a first current output; a second current source having a second current input and a second current output; a first diode having a first input node and a first output node; a switching component having a first switching component node, a second switching component node, and a third switching component node; and a second diode having a second input node and a second…
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