Multi-channel amplifier with chopping

Patent metadata

Field	Value
Publication number	US-9729109-B2
Application number	US-201514823678-A
Country	US
Kind code	B2
Filing date	Aug 11, 2015
Priority date	Aug 11, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Aspects of this disclosure relate to an amplifier with at least two chopper amplifier channels in parallel between a shared input and differential nodes. The amplifier can multiplex outputs of the chopper amplifier channels to provide the output of one or more chopper amplifier channels to the differential nodes at a time. In certain embodiments, this can mask dynamic settling errors.

First claim

What is claimed is:

1. A method of masking dynamic settling errors associated with chopper amplifiers, the method comprising:
amplifying an input signal with at least a first chopper amplifier and a second chopper amplifier arranged in parallel with the first chopper amplifier;
decoupling the first chopper amplifier from an output node for a period of time during which an output voltage of the first chopper amplifier settles to mask dynamic settling errors associated with the output voltage of the first chopper amplifier settling; and
decoupling the second chopper amplifier from the output node for a period of time during which an output voltage of the second chopper amplifier settles to mask dynamic settling errors associated with the output voltage of the second chopper amplifier settling.

2. The method of claim 1 , further comprising repeatedly coupling the first chopper amplifier to the output node and decoupling the first chopper amplifier from the output node at a higher frequency than a frequency of a chop signal provided to the first chopper amplifier.

3. The method of claim 1 , further comprising coupling the first chopper amplifier to the output node for a period of time during which the output voltage of the first chopper amplifier has a substantially constant voltage level after settling.

4. The method of claim 1 , wherein said decoupling the first chopper amplifier comprises decoupling the first chopper amplifier from the output node twice during a period of a chop signal provided to the first chopper amplifier.

5. The method of claim 1 , wherein the first chopper amplifier comprises a feedback amplifier.

6. The method of claim 1 , wherein said amplifying comprises amplifying a combination of the input signal and a zero-order hold signal.

7. The method of claim 1 , wherein the output voltage of the first chopper amplifier has a settling time requirement of at least one sixth of a period of a first chop signal provided to the first chopper amplifier, and wherein the output voltage of the second chopper amplifier has a settling time requirement of at least one sixth of a period of a second chop signal provided to the second chopper amplifier.

8. The method of claim 1 , further comprising alternatingly coupling a third chopper amplifier to and decoupling the third chopper amplifier from the output node, and wherein said amplifying includes amplifying the input signal with the third chopper amplifier.

9. An apparatus for amplifying an input signal and masking dynamic settling errors associated with chopper amplifiers, the apparatus comprising:
a first chopper amplifier configured to amplify an input signal;
a second chopper amplifier configured to amplify the input signal;
differential output nodes configured to provide a differential voltage; and
a switch network configured to:
decouple the first chopper amplifier from the differential output nodes for a duration of time during which an output voltage of first chopper amplifier settles; and
decouple the second chopper amplifier from the differential output nodes for a duration of time during which an output voltage of second chopper amplifier settles,

wherein the output voltage of the first chopper amplifier has a settling time requirement of at least one sixth of a period of a first chop signal of the first chopper amplifier, and
wherein the output voltage of the second chopper amplifier has a settling time requirement of at least one sixth of a period of a second chop signal of the second chopper amplifier.

10. The apparatus of claim 9 , wherein the first chopper amplifier comprises a feedback amplifier.

11. The apparatus of claim 10 , wherein the feedback amplifier comprises a capacitive feedback element disposed between an output terminal of the feedback amplifier and an input terminal of the feedback amplifier.

12. The apparatus of claim 11 , wherein the first chopper amplifier comprises an input chop circuit and an input capacitor coupled between the input chop circuit and the input terminal of the feedback amplifier.

13. The apparatus of claim 9 , wherein the switch network is configured to couple the first chopper amplifier to the output node such that the first chopper amplifier is alternatingly coupled to and decoupled from the output node at about two times a chop frequency of the first chopper amplifier.

14. The apparatus of claim 9 , wherein the second chop signal has the same period as the first chop signal, and wherein the first chop signal and the second chop are offset in time from each other by one quarter of the period of the second chop signal.

15. The apparatus of claim 9 , wherein the switch network is configured such that a continuous output is provided at the differential output nodes.

16. The apparatus of claim 9 , further comprising a third chopper amplifier configured to amplify the input signal, wherein the switch network is configured to couple two of the first chopper amplifier, the second chopper amplifier, and the third chopper amplifier to the differential output nodes concurrently.

17. The apparatus of claim 9 , wherein the switch network is configured to implement an output chop circuit of the first chopper amplifier.

18. An apparatus for amplifying an input signal and masking dynamic settling errors associated with chopper amplifiers, the apparatus comprising:
a first chopper amplifier comprising a first feedback amplifier, the first chopper amplifier configured to amplify the input signal, and the first chopper amplifier further configured to provide a first chopper amplifier output voltage;
a second chopper amplifier comprising a second feedback amplifier, the second chopper amplifier arranged in parallel with the first chopper amplifier, and the second chopper amplifier further configured to provide a second chopper amplifier output voltage; and
means for switching an output node to at least the first chopper amplifier and the second chopper amplifier so as to mask dynamic settling errors associated with the first chopper amplifier output voltage and the second chopper amplifier output voltage.

19. The apparatus of claim 18 , wherein the means for switching is configured to alternatingly couple the first chopper amplifier to and decouple the first chopper amplifier from the output node twice during a chop cycle of the first chopper amplifier.

20. The apparatus of claim 18 , wherein the first feedback amplifier comprises a capacitor electrically coupled between an input terminal of the first feedback amplifier and an output terminal of the first feedback amplifier.

Assignees

• Analog Devices Inc

Inventors

• Shu Marvin L
• Kalb Arthur J

Classifications

• H03F2203/45116

  Feedback coupled to the input of the differential amplifier · CPC title

• H03F1/0205

  in transistor amplifiers · CPC title

• H03F2203/21109

  An input signal being distributed by switching to a plurality of paralleled power amplifiers · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F3/45076

  characterised by the way of implementation of the active amplifying circuit in the differential amplifier · CPC title