Apparatus and methods for multi-channel autozero and chopper amplifiers

Patent metadata

Field	Value
Publication number	US-9496833-B2
Application number	US-201414263214-A
Country	US
Kind code	B2
Filing date	Apr 28, 2014
Priority date	Apr 8, 2014
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

Apparatus and methods for multi-channel autozero and chopper amplifiers are provided herein. In certain configurations, an amplifier includes at least three channels that operate using multiple phases, including at least a non-inverting chop phase, an inverting chop phase, and an autozero phase. The amplifier further includes an autozero and chopping timing control circuit, which at least partially interleaves or staggers timing of the channels' phases. For example, in certain configurations, when one or more of the channels are being autozeroed at a certain time instance, at least some of the remaining channels operate in the non-inverting chop phase or the inverting chop phase.

First claim

What is claimed is:

1. An amplifier comprising:
a plurality of channels comprising:
a first channel;
a second channel; and
a third channel, wherein each of the first channel, the second channel, and the third channel are operable in a plurality of phases including an autozero phase, a non-inverting chop phase, and an inverting chop phase; and

a timing control circuit configured to operate the first channel in the autozero phase during a first time interval and to operate two or more other channels in at least one of the non-inverting chop phase or the inverting chop phase during the first time interval, wherein the timing control circuit is further configured to operate the second channel in the autozero phase during a second time interval and to operate two or more other channels in at least one of the non-inverting chop phase or the inverting chop phase during the second time interval, and wherein the timing control circuit is further configured to operate the third channel in the autozero phase during a third time interval and to operate two or more other channels in at least one of the non-inverting chop phase or the inverting chop phase during the third time interval,
wherein the first time interval, the second time interval, and the third time interval are staggered in time with respect to one another.

2. The amplifier of claim 1 , wherein the plurality of channels comprises four or more channels.

3. An amplifier comprising:
a plurality of channels comprising:
a first channel;
a second channel;
a third channel; and
a fourth channel, wherein each of the first channel, the second channel, the third channel, and the fourth channel are operable in a plurality of phases including an autozero phase, a non-inverting chop phase, and an inverting chop phase; and

a timing control circuit configured to operate the first channel in the autozero phase during a first time interval, to operate the second channel in the autozero phase during a second time interval, to operate the third channel in the autozero phase during a third time interval, and to operate the fourth channel in the autozero phase during a fourth time interval,
wherein the first time interval, the second time interval, the third time interval, and the fourth time interval are staggered in time with respect to one another.

4. The amplifier of claim 3 ,
wherein the plurality of channels further comprises:
a fifth channel; and
a sixth channel, wherein the fifth channel and the sixth channel are operable in the plurality of phases including the autozero phase, the non-inverting chop phase, and the inverting chop phase; and

wherein the timing control circuit is further configured to operate the fifth channel in the autozero phase during a fifth time interval, and to operate the sixth channel in the autozero phase during a sixth time interval,
wherein the first time interval, the second time interval, the third time interval, the fourth time interval, the fifth time interval, and the sixth time interval are staggered in time with respect to one another.

5. The amplifier of claim 4 , wherein the timing control circuit is further configured to operate the first channel in the autozero phase during a seventh time interval that is after the first time interval, wherein the first and second time intervals are partially overlapping in time, wherein the second and third time intervals are partially overlapping in time, wherein the third and fourth time intervals are partially overlapping in time, wherein the fourth and fifth time intervals are partially overlapping in time, wherein the fifth and sixth time intervals are partially overlapping in time, wherein the sixth and seventh time intervals are partially overlapping in time.

6. The amplifier of claim 1 , wherein at least one of the plurality of channels operates in the non-inverting chop phase or the inverting chop phase at any given time that the amplifier is enabled.

7. The amplifier of claim 6 , wherein the amplifier is configured to receive a differential input voltage, wherein the at least one of the plurality of channels operating in the non-inverting chop phase or the inverting chop phase amplifies the differential input voltage.

8. An amplifier comprising:
a plurality of channels comprising:
a first channel;
a second channel; and
a third channel, wherein each of the first channel, the second channel, and the third channel are operable in a plurality of phases including an autozero phase, a non-inverting chop phase, and an inverting chop phase; and

a timing control circuit configured to operate the first channel in the autozero phase during a first time interval, to operate the second channel in the autozero phase during a second time interval, and to operate the third channel in the autozero phase during a third time interval,
wherein the first time interval, the second time interval, and the third time interval are staggered in time with respect to one another,
wherein the first channel, the second channel, and the third channel are configured to share input chopping switches and output chopping switches.

9. An amplifier comprising:
a plurality of channels comprising:
a first channel;
a second channel; and
a third channel, wherein each of the first channel, the second channel, and the third channel are operable in a plurality of phases including an autozero phase, a non-inverting chop phase, and an inverting chop phase; and

a timing control circuit configured to operate the first channel in the autozero phase during a first time interval, to operate the second channel in the autozero phase during a second time interval, and to operate the third channel in the autozero phase during a third time interval,
wherein the first time interval, the second time interval, and the third time interval are staggered in time with respect to one another,
wherein the first channel includes first input chopping switches and first output chopping switches, wherein the second channel includes second input chopping switches and second output chopping switches, and wherein the third channel includes third input chopping switches and third output chopping switches.

10. The amplifier of claim 9 , wherein the timing control circuit is configured to generate a plurality of chopping clock signals that are interleaved in time, wherein a first portion of the plurality of chopping clock signals are configured to control the first input chopping switches and the first output chopping switches, wherein a second portion of the plurality of chopping clock signals are configured to control the second input chopping switches and the second output chopping switches, and wherein a third portion of the plurality of chopping clock signals are configured to control the third input chopping switches and the third output chopping switches.

11. The amplifier of claim 1 , wherein the first channel comprises a first transconductance amplification circuit, wherein the second channel comprises a second transconductance amplification circuit, and wherein the third channel comprises a third transconductance amplification circuit.

12. The amplifier of claim 11 , further comprising at least one node configured to generate a summed current based on a plurality of output currents generated by the plurality of channels.

13. The amplifier of claim 12 , further comprising an output stage configured to convert the summed current to an output voltage of the amplifier.

14. The amplifier of claim 11 , wherein the amplifier is configured to receive a differential input voltage,
wherein the first transconductance amplification circuit is configured

Assignees

• Analog Devices Inc

Inventors

• Kusuda Yoshinori

Classifications

• H03F3/45968

  by offset reduction · CPC title

• H03F3/387 Primary

  with semiconductor devices only · CPC title

• H03F2203/45171

  the input signal being switched to the one or more input terminals of the differential amplifier · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2200/421

  Multiple switches coupled in the output circuit of an amplifier are controlled by a circuit · CPC title