Apparatus and methods for autozero amplifiers

Patent metadata

Field	Value
Publication number	US-9294037-B2
Application number	US-201414223650-A
Country	US
Kind code	B2
Filing date	Mar 24, 2014
Priority date	Mar 24, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of transconductance stages comprising:
a first transconductance stage;
a second transconductance stage; and
a third transconductance stage, wherein each of the first transconductance stage, the second transconductance stage, and the third transconductance stage have an autozero mode and an amplification mode;

an autozero timing control circuit configured to operate the first transconductance stage in the autozero mode during a first time interval, to operate the second transconductance stage in the autozero mode during a second time interval, and to operate the third transconductance stage in the autozero mode during a third time interval,
wherein the first time interval, the second time interval, and the third time interval are staggered in time,
wherein the autozero timing control circuit is further configured to control an autozero sequence of the plurality of transconductance stages, wherein the autozero timing control circuit comprises a randomization circuit configured to randomize the autozero sequence to have a random or pseudo random order.

2. The apparatus of claim 1 , wherein at least one transconductance stage of the plurality of transconductance stages is configured to provide amplification during the first time interval, during the second time interval, and during the third time interval.

3. The apparatus of claim 2 , wherein the autozero timing control circuit is further configured to operate the second and third transconductance stages in the amplification mode during the first time interval, wherein the autozero timing control circuit is further configured to operate the first and third transconductance stages in the amplification mode during the second time interval, and wherein the autozero timing control circuit is further configured to operate the first and second transconductance stages in the amplification mode during the third time interval.

4. An apparatus comprising:
a plurality of transconductance stages comprising:
a first transconductance stage;
a second transconductance stage; and
a third transconductance stage, wherein each of the first transconductance stage, the second transconductance stage, and the third transconductance stage have an autozero mode and an amplification mode;

an autozero timing control circuit configured to operate the first transconductance stage in the autozero mode during a first time interval, to operate the second transconductance stage in the autozero mode during a second time interval, and to operate the third transconductance stage in the autozero mode during a third time interval,
wherein the first time interval, the second time interval, and the third time interval are staggered in time;
a differential input voltage terminal;
a first pair of input switches electrically connected between the differential input voltage terminal and a differential input of the first transconductance stage;
a second pair of input switches electrically connected between the differential input voltage terminal and a differential input of the second transconductance stage; and
a third pair of input switches electrically connected between the differential input voltage terminal and a differential input of the third transconductance stage.

5. The apparatus of claim 4 , wherein the autozero timing control circuit is further configured to control an autozero sequence of the plurality of transconductance stages, wherein the autozero sequence has a fixed order.

6. The apparatus of claim 4 , further comprising:
an output voltage terminal;
an output stage including an input and an output, wherein the output is electrically connected to the output voltage terminal;
a first output switch electrically connected between an output of the first transconductance stage and the input of the output stage, wherein the autozero timing control circuit is further configured to open the first output switch when the first transconductance stage operates in the autozero mode, and to close the first output switch when the first transconductance stage operates in the amplification mode;
a second output switch electrically connected between an output of the second transconductance stage and the input of the output stage, wherein the autozero timing control circuit is further configured to open the second output switch when the second transconductance stage operates in the autozero mode, and to close the second output switch when the second transconductance stage operates in the amplification mode; and
a third output switch electrically connected between an output of the third transconductance stage and the input of the output stage, wherein the autozero timing control circuit is further configured to open the third output switch when the third transconductance stage operates in the autozero mode, and to close the third output switch when the third transconductance stage operates in the amplification mode.

7. An apparatus comprising:
a plurality of transconductance stages comprising:
a first transconductance stage;
a second transconductance stage; and
a third transconductance stage, wherein each of the first transconductance stage, the second transconductance stage, and the third transconductance stage have an autozero mode and an amplification mode;

an autozero timing control circuit configured to operate the first transconductance stage in the autozero mode during a first time interval, to operate the second transconductance stage in the autozero mode during a second time interval, and to operate the third transconductance stage in the autozero mode during a third time interval,
wherein the first time interval, the second time interval, and the third time interval are staggered in time,
wherein the first transconductance stage comprises a primary transconductor, an auxiliary transconductor, and an input offset correction capacitor, wherein when the first transconductance stage operates in the amplification mode the primary transconductor provides amplification, and wherein when the first transconductance stage operates in the autozero mode the auxiliary transconductor corrects for an input offset voltage of the primary transconductor by storing an offset correction voltage across the input offset correction capacitor.

8. The apparatus of claim 1 , wherein the plurality of transconductance stages further comprises a fourth transconductance stage, wherein the autozero timing control circuit is further configured to operate the fourth transconductance stage in the autozero mode during a fourth time interval, wherein the first time interval, the second time interval, the third time interval, and the fourth time interval are staggered in time.

9. The apparatus of claim 1 , wherein the plurality of transconductance stages comprises four or more transconductance stages.

10. A method of electronic amplification comprising:
providing a differential input voltage to an autozero amplifier comprising a plurality of transconductance stages, wherein the plurality of transconductance stages comprise a first transconductance stage, a second transconductance stage, and a third transconductance stage;
controlling timing of the plurality of transconductance stages using an autozero timing control circuit;
autozeroing the first transconductance stage during a first time interval using the autozero timing control circuit;
autozeroing the second transconductance stage during a second time interval using the autozero timing control circuit;
autozeroing the third transconductance stage during a third time interval using the autozero timing control circuit,
wherein the first time interval, the second time interval, and the third time

Assignees

• Analog Devices Global

Inventors

• Maurino Roberto S
• Nittala Venkata Aruna Srikanth
• Kawle Abhilasha
• Rajasekhar Sanjay

Classifications

• H03F2200/234

  the input amplifying stage being one or more operational amplifiers · CPC title

• H03F3/45076

  characterised by the way of implementation of the active amplifying circuit in the differential amplifier · CPC title

• H03F2203/45288

  Differential amplifier with circuit arrangements to enhance the transconductance · CPC title

• H03F1/02 Primary

  Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title