Construction of a hall-effect sensor in a buried isolation region

Patent metadata

Field	Value
Publication number	US-9728581-B2
Application number	US-201514932949-A
Country	US
Kind code	B2
Filing date	Nov 4, 2015
Priority date	Nov 4, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

First claim

What is claimed is:

1. A method of forming an integrated circuit, comprising the steps:
providing a substrate comprising a p-type semiconductor material;
implanting n-type dopants into the substrate to concurrently form a first n-type isolation layer and a second n-type isolation layer, the first n-type isolation layer providing a Hall plate of a Hall sensor of the integrated circuit, the second n-type isolation layer providing an isolation layer for an NMOS transistor of the integrated circuit;
implanting p-type dopants into the substrate to concurrently form a first shallow p-type well and a second shallow p-type well, the first shallow p-type well being in the first n-type isolation layer and located over, and extending to, the Hall plate, the second shallow p-type well being in the second n-type isolation layer and located under an area for the NMOS transistor;
forming the NMOS transistor over the second shallow p-type well;
forming a PMOS transistor of the integrated circuit; and
forming at least one of a current source electrically coupled to the Hall sensor and a voltage sensor electrically coupled to the Hall sensor,
wherein the implanting n-type dopants into the substrate concurrently to form first shallow n-type wells and second shallow n-type well, the first shallow n-type wells providing electrical connections to the Hall plate and the second shallow n-type well located in an area for the PMOS transistor.

2. The method of claim 1 , comprising implanting n-type dopants into the substrate to concurrently form n-type contact regions and NSD regions, the n-type contact regions being formed in the first shallow n-type wells and the NSD regions being formed in the NMOS transistor.

3. The method of claim 1 , wherein implanting the n-type dopants into the substrate to concurrently form the first n-type isolation layer and the second n-type isolation layer comprises implanting phosphorus at 1000 kilo-electron volts (keV) to 2000 keV with a dose of 5×10 12 cm −2 to 2×10 13 cm −2 .

4. The method of claim 1 , wherein implanting the p-type dopants into the substrate to concurrently form the first shallow p-type well and the second shallow p-type well comprises implanting phosphorus at 200 kilo-electron volts (keV) to 500 keV with a dose of 2×10 13 cm −2 to 5×10 13 cm −2 .

5. The method of claim 1 , comprising:
forming an isolation mask over the substrate prior to implanting the n-type dopants into the substrate to concurrently form the first n-type isolation layer and the second n-type isolation layer, the isolation mask including blocking elements in an area for the Hall plate, the isolation mask being free of blocking elements in the area for the second n-type isolation layer;
implanting the n-type dopants into the substrate to concurrently form the first n-type isolation layer and the second n-type isolation layer while the isolation mask is in place; and
removing the isolation mask.

6. The method of claim 1 , comprising:
forming a compensation mask over the substrate after implanting the n-type dopants into the substrate to concurrently form the first n-type isolation layer and the second n-type isolation layer, the compensation mask exposing an area for the Hall plate and covering an area for the NMOS transistor and an area for the PMOS transistor;
implanting p-type dopants into the substrate while the isolation mask is in place to form a compensation well which compensates the n-type dopants in the Hall plate, the Hall plate remaining n-type after formation of the compensation well; and
removing the compensation mask.

7. The method of claim 1 , comprising forming a circuit component over the Hall plate, at least a portion of the circuit component being disposed in the first shallow p-type well.

Assignees

• Texas Instruments Inc

Inventors

• Green Keith Ryan
• Aggarwal Rajni J
• Sharma Ajit

Classifications

• H01L43/04

  Electricity · mapped topic

• H01L27/22 Primary

  Electricity · mapped topic

• H01L43/065

  Electricity · mapped topic

• H01L43/14

  Electricity · mapped topic

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title