Semiconductor device including image sensor and method of forming the same
US-2024379711-A1 · Nov 14, 2024 · US
Semiconductor device manufacturing method and semiconductor device manufactured using the same
US2024395745A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2024395745-A1 |
| Application number | US-202418433177-A |
| Country | US |
| Kind code | A1 |
| Filing date | Feb 5, 2024 |
| Priority date | May 24, 2023 |
| Publication date | Nov 28, 2024 |
| Grant date | — |
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Abstract
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The present disclosure provides a semiconductor device manufacturing method that includes forming a lower chip and an upper chip, and bonding the lower chip and the upper chip to each other. The forming of the lower chip includes providing a lower substrate, sequentially forming a lower interlayer insulating film and a pre-lower adhesive film, etching portions of the pre-lower adhesive film and the lower interlayer insulating film to form a lower trench, forming, using a sputtering process, a first lower seed film and a second lower seed film. The forming of the upper chip includes providing an upper substrate, sequentially forming an upper interlayer insulating film and a pre-upper adhesive film, etching portions of the pre-upper adhesive film and the upper interlayer insulating film to form an upper trench, forming, using the sputtering process, a first upper seed film and a second upper seed film.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device manufacturing method, comprising: forming a lower chip and an upper chip; and bonding the lower chip and the upper chip to each other; wherein the forming of the lower chip comprises: providing a lower substrate; sequentially forming, on the lower substrate, a lower interlayer insulating film and a pre-lower adhesive film; etching a first portion of the pre-lower adhesive film and a second portion of the lower interlayer in…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2024395745A1 cover?
- The present disclosure provides a semiconductor device manufacturing method that includes forming a lower chip and an upper chip, and bonding the lower chip and the upper chip to each other. The forming of the lower chip includes providing a lower substrate, sequentially forming a lower interlayer insulating film and a pre-lower adhesive film, etching portions of the pre-lower adhesive film and…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10F39/807. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 28 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).