Bipolar transistor device

Patent metadata

Field	Value
Publication number	US-9728530-B1
Application number	US-201615384736-A
Country	US
Kind code	B1
Filing date	Dec 20, 2016
Priority date	Dec 20, 2016
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

First claim

What is claimed is:

1. A bipolar transistor device comprising:
a substrate; and
at least one first transistor unit comprising:
a first doped well of first conductivity type arranged in said substrate;
at least one first fin-based structure comprising:
a plurality of first doped fins uniformly arranged in said first doped well, and arranged along a first direction, and each said first doped fin has a first doped region of said first conductivity type and two first heavily doped regions of second conductivity type, and each said first doped region is arranged between said two first heavily doped regions corresponded thereof, and said first doped regions and said first heavily doped regions are arranged in said first doped well and protruded up from a surface of said substrate; and
a first gate strip arranged on tops and sidewalls of said first doped regions and said surface of said substrate, and arranged along a second direction intersecting said first direction, and said first gate strip is floating; and

at least one second fin-based structure comprising:
a plurality of second doped fins uniformly arranged in said first doped well, and arranged along said first direction, and each said second doped fin has a second doped region of said first conductivity type and two second heavily doped regions of said second conductivity type, and each said second doped region is arranged between said two second heavily doped regions corresponded thereof, and said second doped regions and said second heavily doped regions are arranged in said first doped well and protruded up from said surface of said substrate; and
a second gate strip arranged on tops and sidewalls of said second doped regions and said surface of said substrate, and arranged along said second direction, and said second gate strip is floating, and said first heavily doped regions, said second heavily doped regions and said first doped well form a plurality of first bipolar junction transistors (BJTs), and said first heavily doped regions are coupled to a high voltage terminal, and said second heavily doped regions are coupled to a low voltage terminal, and voltages of said high voltage terminal and said low voltage terminal bias said first BJTs to generate a plurality of first electrostatic discharge (ESD) currents through said first BJTs.

2. The bipolar transistor device according to claim 1 , wherein said first conductivity type is a P type and said second conductivity type is an N type; and said first conductivity type is an N type and said second conductivity type is a P type.

3. The bipolar transistor device according to claim 1 , wherein said second direction is perpendicular to said first direction.

4. The bipolar transistor device according to claim 1 , wherein said first fin-based structure further comprises two first contacts respectively arranged on sidewalls and tops of said first heavily doped regions at two opposite sides of said first doped regions and said surface of said substrate, and arranged along said second direction, and said first heavily doped regions are coupled to said high voltage terminal via said first contacts; and said second fin-based structure further comprises two second contacts respectively arranged on sidewalls and tops of said second heavily doped regions at two opposite sides of said second doped regions and said surface of said substrate, and arranged along said second direction, and said second heavily doped regions are coupled to said low voltage terminal via said second contacts.

5. The bipolar transistor device according to claim 1 , wherein said first gate strip and said second gate strip comprise polysilicon.

6. The bipolar transistor device according to claim 1 , wherein said at least one first fin-based structure is a plurality of said first fin-based structures, and said at least one second fin-based structure is a plurality of said second fin-based structures, and said first fin-based structures and said second fin-based structures are arranged in an alternate way.

7. The bipolar transistor device according to claim 1 , wherein said at least one first fin-based structure is two said first fin-based structures, and said first transistor unit further comprises a first doped area of said second conductivity type arranged in said first doped well, and said second fin-based structure is arranged between said first fin-based structures, and said second heavily doped regions and said second doped regions are arranged in said first doped area, and said second gate strip is arranged between said first gate strips, and said second gate strip is connected with said first gate strips.

8. The bipolar transistor device according to claim 7 , wherein said first doped area is a doped well.

9. The bipolar transistor device according to claim 7 , further comprising at least one second transistor unit, and said at least one first transistor unit is two said first transistor units, and said second transistor unit further comprises:
a second doped well of said second conductivity type arranged in said substrate;
a second doped area of said first conductivity type arranged in said second doped well;
two third fin-based structures each comprising:
a plurality of third doped fins uniformly arranged in said second doped well, and arranged along said first direction, and each said third doped fin has a third doped region of said second conductivity type and two third heavily doped regions of said first conductivity type, and each said third doped region is arranged between said two third heavily doped regions corresponded thereof, and said third doped regions and said third heavily doped regions are arranged in said second doped well and protruded up from said surface of said substrate, and said third heavily doped regions are coupled to said low voltage terminal; and
a third gate strip arranged on tops and sidewalls of said third doped regions and said surface of said substrate, and arranged along said second direction, and said third gate strip is floating; and

a fourth fin-based structure comprising:
a plurality of fourth doped fins uniformly arranged in said second doped area, and arranged along said first direction, and each said fourth doped fin has a fourth doped region of said first conductivity type and two fourth heavily doped regions of said second conductivity type, and each said fourth doped region is arranged between said two fourth heavily doped regions corresponded thereof, and said fourth doped regions and said fourth heavily doped regions are arranged in said second doped area and protruded up from said surface of said substrate, and said fourth heavily doped regions are coupled to said high voltage terminal; and
a fourth gate strip arranged on tops and sidewalls of said fourth doped regions and said surface of said substrate, and arranged along said second direction, and said fourth gate strip is floating,
and said fourth gate strip is arranged between said third gate strips, and said fourth gate strip is connected with said third gate strips, and said third heavily doped regions, said fourth heavily doped regions, said second doped well and said second doped area form a plurality of second BJTs, and said voltages of said high voltage terminal and said low voltage terminal bias said second BJTs to generate a plurality of second ESD currents through said second BJTs, and said first doped wells are adjacent to said second doped well in an alternate way, and said first doped areas are adjacent to said second doped area in an alternate way.

10. The bipolar transistor device according to claim 9 , wherein said third fin-based structure further comprises two third contacts respectively arranged on sidewalls and tops o

Assignees

• Amazing Microelectronic Corp

Inventors

• Ker Ming-Dou
• Wu Woei-Lin
• Peng James Jeng-Jie
• Jiang Ryan Hsin-Chin

Classifications

• H01L29/36

  Electricity · mapped topic

• H01L27/0259 Primary

  Electricity · mapped topic

• H01L29/732

  Electricity · mapped topic

• H01L27/0826

  Electricity · mapped topic

• H10D10/40

  Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)} · CPC title