Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection

Patent metadata

Field	Value
Publication number	US-9502883-B2
Application number	US-201514795854-A
Country	US
Kind code	B2
Filing date	Jul 9, 2015
Priority date	Sep 28, 2012
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) protection device, comprising:
a plurality of semiconductor fins extending from a substrate with a gate electrode disposed over the plurality of semiconductor fins;
a source region and a drain region disposed in each of the semiconductor fins on opposite sides of the gate electrode, wherein the source region and the gate electrode are electrically coupled to one or more integrated circuit (IC) nodes having a same ground reference potential, wherein and the drain region is electrically coupled to a circuit node disposed between an I/O of the IC and core circuitry of the IC coupled to the I/O, and wherein the drain region has an uppermost surface; and
a lightly doped extended drain region disposed in the semiconductor fins and spacing apart the gate electrode from the drain regions by an amount greater than a spacing between the gate electrode and the source regions, wherein the lightly doped extended drain region has an uppermost surface approximately co-planar with the uppermost surface of the drain region.

2. The device of claim 1 , further comprising:
a control gate disposed over the semiconductor fins between the gate electrode and the drain regions, wherein the control gate is capacitively coupled to at least a portion of the lightly doped extended drain region and electrically insulated from the gate electrode.

3. The microelectronic device of claim 2 , wherein the control gate is to control charge carrier depletion or accumulation within the lightly doped extended drain region to adjust a snapback holding voltage of the device.

4. The device of claim 2 , further comprising a control gate voltage source coupled to the control gate, wherein the control gate voltage source is to set the control gate to a predetermined control gate voltage potential other than the gate electrode reference potential.

5. The device of claim 4 , wherein the control gate and the gate electrode are of a same material and are capacitively coupled to the semiconductor fins through a same gate dielectric, wherein the control gate is spaced apart from the drain region by an amount less than a spacing between the gate electrode and the control gate.

6. The device of claim 1 , wherein the semiconductor comprises silicon doped p-type below the gate electrode, wherein the source and drain regions are heavily doped n-type, wherein the lightly doped extended drain region is doped n-type to 10 16 cm −3 -10 20 cm −3 , and wherein on-state current of the device is at least 0.4 A/μm of channel width or a drain voltage of 11V.

7. An integrated circuit device, comprising:
a plurality of core circuits disposed over a substrate;
a plurality of I/Os disposed over the substrate, wherein each of the core circuits is coupled to at least one of the I/Os to interface the core circuits with one or more external devices;
a plurality of electrostatic discharge (ESD) protection devices, each ESD protection device coupled to a node disposed between at least one of the core circuits and at least one of the I/O pins or pads, wherein each of the ESD protection devices comprise an extended drain non-planar metal-oxide-semiconductor field effect transistor (MOSFET) including:
a plurality of semiconductor fins, each having a source region and drain region disposed on opposite sides of a gate electrode disposed over the semiconductor fins, wherein the drain region has an uppermost surface; and
a control gate disposed over the semiconductor fins capacitively coupled to a lightly doped extended drain region disposed in the semiconductor fins between the drain region and the gate electrode, wherein the lightly doped extended drain region has an uppermost surface approximately co-planar with the uppermost surface of the drain region; and

a plurality of control gate voltage sources coupled to the ESD protection devices, wherein ones of the control gate voltage sources are coupled to separate control gates.

8. The integrated circuit device of claim 7 , wherein the control gate voltage sources are independently controllable to predetermined voltage potentials other than the ground potential.

9. The integrated circuit device of claim 8 , wherein the predetermined voltage potentials are between 0.5V and 1.2V.

10. The integrated circuit device of claim 8 , wherein the predetermined voltage potentials adjust a snapback voltage of the ESD protection device based on a characteristic of the core circuit to which the ESD protection device is coupled.

11. The integrated circuit device of claim 10 , wherein the source, drain and lightly doped extended drain regions are n-type, the gate electrode and the source region are coupled to circuit nodes at ground potential of the core circuits, and the first and second control gate potentials are between 0V and 1.2V.

12. The integrated circuit device of claim 10 , wherein the plurality of circuits further comprises:
a low voltage circuit coupled to a first of the I/Os and to a first of the ESD protection devices; and
a high voltage circuit coupled to a second of the I/Os and to a second of the ESD protection devices, wherein the first ESD protection device has a first control gate coupled to a first control gate voltage source and the second ESD protection device has a second control gate coupled to a second control gate voltage source that is at a different control gate potential than the first control gate voltage source.

13. The integrated circuit device of claim 11 , wherein the second control gate voltage source is at a control gate voltage potential that increases the resistance of the lightly doped extended drain region of the second ESD protection device relative to that of the first ESD protection device.

14. The integrated circuit device of claim 12 , wherein the low voltage circuit and high voltage circuit both further comprise one or more non-planar MOSFET, and wherein at least one of the non-planar MOSFETs in the high voltage circuit includes an extended drain region having a higher source-drain resistance that of any of the non-planar MOSFETs in the low voltage circuit.

15. The integrated circuit device of claim 12 , wherein the low voltage circuit is operable at voltages no greater than 1.5V and wherein the high voltage circuit is operable at voltages between 1.5 and 3.3V.

16. A mobile computing device, comprising:
a processor with core circuitry coupled to an I/O and a non-planar ggNMOS ESD protection device disposed there between, wherein the ESD protection device includes a plurality of semiconductor fins having a lightly doped extended drain region disposed on a first side of a gate electrode, and spacing the gate electrode farther from a heavily doped drain region of the semiconductor fin than a spacing between the gate electrode and a source region of the semiconductor fin, wherein the heavily doped drain region has an uppermost surface, and wherein the lightly doped extended drain region has an uppermost surface approximately co-planar with the uppermost surface of the heavily doped drain region;
a display screen;
an RF transmitter or receiver; and
an antenna.

17. The mobile computing device of claim 16 , wherein the non-planar ggNMOS ESD protection device further comprises a control gate capacitively coupled to the lightly doped extended drain region, wherein the control gate is electrically insulated from the gate electrode and at a different potential than the gate electrode.

18. The mobile computing device of claim 17 , wherein the processor and RF transmitter or receiver are on a single integrat

Assignees

• Intel Corp

Inventors

• Ahsan Akm
• Hafez Walid M

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D89/813

  specially adapted to provide an electrical current path other than the field-effect induced current path · CPC title

• H10D89/60 Primary

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title