Multiple bond via arrays of different wire heights on a same substrate

Patent metadata

Field	Value
Publication number	US-9728527-B2
Application number	US-201514925807-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Nov 22, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

First claim

What is claimed is:

1. A method, comprising:
obtaining a substrate;
feeding wire from a wire spool control head for:
forming a first bond via array of first wire bond wires (“first wires”) extending from a surface of the substrate having rows and columns of the first wires; and
forming a second bond via array of second wire bond wires (“second wires”) extending from the surface of the substrate having rows and columns of the second wires;

wherein the first bond via array and the second bond via array are external to the substrate;
wherein the first bond via array is disposed within a region of the second bond via array;
wherein the first wires of the first bond via array are of a first height; and
wherein the second wires of the second bond via array are of a second height greater than the first height for a package-on-package configuration;
wherein a first pitch of the first wires of the first bond via array is less than 0.5 mm; and
wherein a second pitch of the second wires of the second bond via array is a range of approximately 0.01 to 0.5 mm.

2. The method according to claim 1 , further comprising:
coupling a first die to the first bond via array; and
coupling a second die to the second bond via array;
wherein the second die is disposed over the first die.

3. The method according to claim 2 , wherein the first die and at least a portion of the second die are located within a perimeter of the second bond via array.

4. The method according to claim 2 , further comprising coupling opposing surfaces of the first die and the second die to one another.

5. The method according to claim 2 , further comprising attaching the first wires of the first bond via array and the second wires of the second bond via array by fusion bonding to the surface of the substrate.

6. The method according to claim 2 , wherein a portion of the second wires are formed as angled wires with an angle less than approximately 90 degrees with reference to the surface of the substrate.

7. The method according to claim 2 , wherein the first die and the second die are coupled to one another.

8. The method according to claim 7 , wherein the first die and the second die are coupled to one another by die-to-die interconnects.

9. The method according to claim 7 , wherein the first die and the second die are coupled to one another by a spacer layer.

10. The method according to claim 7 , wherein the first die and the second die are coupled to one another by a redistribution layer.

11. The method according to claim 2 , wherein the package-on-package configuration comprises:
the first die coupled to first ends of the first wires on a backside surface of the first die as a downward facing die; and
the second die coupled to second ends of the second wires on a backside surface of the second die as an upward facing die.

12. The method according to claim 2 , wherein the package-on-package configuration comprises:
the first die coupled to first ends of the first wires on a backside surface of the first die as a downward facing die; and
the second die coupled to second ends of the second wires on a backside surface of the second die as a downward facing die.

13. The method according to claim 2 , wherein the package-on-package configuration comprises:
the first die coupled to first ends of the first wires on a front side surface of the first die as an upward facing die; and
the second die coupled to second ends of the second wires on a backside surface of the second die as a downward facing die; and
wherein a backside surface of the first die is coupled to the backside surface of the second die by die-to-die interconnects.

14. The method according to claim 1 , wherein:
the first pitch of the first wires of the first bond via array is a first wire diameter of the first wires; and
the second pitch of the second wires of the second bond via array is a second wire diameter of the second wires.

15. The method according to claim 14 , wherein the first wire diameter is smaller than the second wire diameter.

16. The method according to claim 14 , wherein a portion of at least one of the first wires or the second wires includes angled wires thereof.

17. The method according to claim 1 , further comprising:
coupling an integrated circuit die to the first bond via array;
coupling a redistribution layer to the second bond via array; and
wherein the redistribution layer is disposed over the integrated circuit die.

18. A method, comprising:
feeding wire from a wire spool control head for:
forming a first bond via array of first wire bond wires extending from a surface of a die having rows and columns of the first wire bond wires; and
forming a second bond via array of second wire bond wires extending from a surface of a redistribution layer having rows and columns of the second wire bond wires;

wherein the first bond via array and the second bond via array are external to the die and the redistribution layer, respectively;
wherein the first bond via array is disposed within a region of the second bond via array;
wherein the first wire bond wires of the first bond via array are of a first height;
wherein the second wire bond wires of the second bond via array are of a second height greater than the first height for a package-on-package configuration;
wherein a first pitch of the first wire bond wires of the first bond via array is in less than 0.5 mm; and
wherein a second pitch of the second wire bond wires of the second bond via array is a range of approximately 0.01 to 0.5 mm.

19. A method, comprising:
feeding wire from a wire spool control head for:
forming a first bond via array of first wire bond wires extending from a surface of a first die having rows and columns of the first wire bond wires; and
forming a second bond via array of second wire bond wires extending from a surface of a second die having rows and columns of the second wire bond wires;

wherein the first bond via array and the second bond via array are external to the first die and the second die, respectively;
wherein the first bond via array is disposed within a region of the second bond via array;
wherein the first wire bond wires of the first bond via array are of a first height;
wherein the second wire bond wires of the second bond via array are of a second height greater than the first height for a package-on-package configuration;
wherein a first pitch of the first wire bond wires of the first bond via array is less than 0.5 mm; and
wherein a second pitch of the second wire bond wires of the second bond via array is a range of approximately 0.01 to 0.5 mm.

20. The method according to claim 1 , wherein the first wires and the second wires are made of different materials to provide at least one of different conductivities or e-moduli as between the first wires and the second wires.

Assignees

• Invensas Corp

Inventors

• Uzoh Cyprian Emeka
• Katkar Rajesh

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title