Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9728460-B2
Application number	US-201615278332-A
Country	US
Kind code	B2
Filing date	Sep 28, 2016
Priority date	Oct 30, 2015
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

It is prevented that when a predetermined number of semiconductor chips having transistors are manufactured from one semiconductor wafer, manufacturing cost of a semiconductor device is increased due to excess semiconductor chips manufactured from the semiconductor wafer. A first bipolar transistor including a first emitter region having a first area is formed in a first chip formation region in an exposure region that can be exposed by one exposure step, and a second bipolar transistor including a second emitter region having a second area different from the first area is formed in a second chip formation region in the exposure region.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a semiconductor substrate having a first conductivity type;
(b) forming a first semiconductor region having a second conductivity type different from the first conductivity type over a top of the semiconductor substrate;
(c) forming a second semiconductor region having the first conductivity type and a third semiconductor region having the first conductivity type over a top of the first semiconductor region; and
(d) dividing the semiconductor substrate into individual pieces, thereby forming a first semiconductor chip including a first transistor including the semiconductor substrate, the first semiconductor region, and the second semiconductor region, and a second semiconductor chip including a second transistor including the semiconductor substrate, the first semiconductor region, and the third semiconductor region;
wherein area of the second semiconductor region is smaller than area of the third semiconductor region in plan view.

2. The method according to claim 1 , wherein in the step (c), an impurity having the first conductivity type is introduced into the top of the semiconductor substrate, thereby the second semiconductor region and the third semiconductor region are formed, and
wherein the method further comprises the step of:
(d1) after the step (c), heating the semiconductor substrate with a vertical furnace.

3. The method according to claim 1 , wherein an amplification factor of the first transistor is smaller than an amplification factor of the second transistor.

4. The method according to claim 1 , wherein the step (c) further comprises the steps of:
(c1) forming an insulating film covering the top of the semiconductor substrate;
(c2) forming a photosensitive film over the insulating film;
(c3) performing exposure and development of the photosensitive film, thereby removing part of the photosensitive film to expose a top of the insulating film;
(c4) after the step (c3), processing the insulating film with the photosensitive film as a mask, thereby exposing the top of the semiconductor substrate; and
(c5) implanting an impurity having the first conductivity type into the top of the semiconductor substrate, thereby forming the second semiconductor region and the third semiconductor region,
wherein in the step (c5), the second semiconductor region and the third semiconductor region are formed in a region that can be exposed by one-time exposure performed in the step (c3).

5. The method according to claim 1 , wherein in the step (d), a plurality of semiconductor chips each being the first semiconductor chip and a plurality of semiconductor chips each being the second semiconductor chip are formed.

6. The method according to claim 1 , wherein a semiconductor wafer including the semiconductor substrate has a diameter larger than six inches.

7. The method according to claim 2 ,
wherein the vertical furnace has a furnace core tube that extends in a direction perpendicular to a horizontal plane, and
wherein in the step (d1), the semiconductor substrate is heated, the semiconductor substrate being disposed in the furnace core tube while a top of the semiconductor substrate is parallel to the horizontal plane.

8. The method according to claim 1 ,
wherein depth of the first semiconductor region is deeper than depth of each of the second semiconductor region and the third semiconductor region, and
wherein each of the first transistor and the second transistor is a bipolar transistor.

9. The method according to claim 1 , wherein the first semiconductor chip does not include the second transistor, and the second semiconductor chip does not include the first transistor.

10. The method according to claim 1 , wherein the second semiconductor region is a first emitter region of the first transistor, and the third semiconductor region is a second emitter region of the second transistor.

11. The method according to claim 2 , wherein in the step (d1), the semiconductor substrate is heated, thereby the impurity having the first conductivity type is diffused.

Assignees

• Renesas Electronics Corp

Inventors

• Maeda Shinichi

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H01L27/082

  Electricity · mapped topic

• H01L21/8222 Primary

  Electricity · mapped topic

• H01L21/324

  Electricity · mapped topic