Methods of forming memory arrays and semiconductor constructions

Patent metadata

Field	Value
Publication number	US-9230968-B2
Application number	US-201414569337-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Aug 21, 2012
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.

First claim

We claim:

1. A method of forming a memory array, comprising:
providing a base comprising a first semiconductive material, the base having an memory array region and a peripheral region;
forming a planar recessed upper surface of the array region, the upper surface of the array region being recessed relative to uppermost surfaces of the base in the peripheral region;
forming a heavily-doped region within the first semiconductor material in the array region;
epitaxially growing a second semiconductor material over the first semiconductor material; the second semiconductor material being in situ doped during the epitaxial growth to form a stack of doped regions over the heavily-doped region;
forming first trenches through the second semiconductor material; the first trenches extending along a first direction, and penetrating entirely through the heavily-doped region;
forming second trenches through the second semiconductor material, the second trenches extending along a second direction which intersects the first direction, and not penetrating entirely through the heavily-doped region; the first and second trenches together patterning the second semiconductor material into a plurality of vertically-extending pillars comprising the stacked doped regions, and patterning the heavily-doped region into a plurality of buried lines under the pillars; the buried lines electrically interconnecting pluralities of the pillars to one another; and
forming data storage devices over the vertically-extending pillars and electrically coupled with top doped regions of the stacked doped regions.

2. The method of claim 1 wherein the first trenches are formed before the second trenches.

3. The method of claim 1 wherein the second trenches are formed before the first trenches.

4. The method of claim 1 wherein the heavily-doped region is n-type.

5. The method of claim 1 wherein the heavily-doped region is p-type.

6. The method of claim 1 wherein the stack comprises a lower source/drain region, a channel region and an upper source/drain region in ascending order from the heavily-doped region; and further comprising:
forming gatelines along the pillars, the gatelines extending across pluralities of channel regions; each pillar being incorporated into a vertical transistor uniquely addressed through a combination of a buried line and a gateline; and
forming the data storage devices over the vertical transistors and electrically coupled with the top source/drain regions of the vertical transistors.

7. The method of claim 6 wherein the data storage devices are capacitors and the memory array is a DRAM array with individual memory cells of the array comprising one of the vertical transistors coupled with one of the capacitors.

8. The method of claim 1 wherein the data storage devices are memory cells, and wherein the vertically-extending pillars are incorporated into access devices electrically coupled with the memory cells.

9. The method of claim 8 wherein the stack comprises a lower emitter/collector region, a base region and an upper emitter/collector region in ascending order from the heavily doped region; and wherein the vertical pillars are incorporated into BJT access devices.

10. The method of claim 8 wherein the stack comprises a lower source/drain region, a channel region and an upper source/drain region in ascending order from the heavily-doped region; and wherein the vertical pillars are incorporated into vertical transistor access devices.

11. The method of claim 8 wherein the stack comprises a first diode region, an intrinsic region and a second diode region in ascending order from the heavily-doped region; and wherein the vertical pillars are incorporated into diode access devices.

12. The method of claim 1 wherein the heavily-doped region is formed by:
implanting conductivity enhancing dopant into the first semiconductor material in combination with one or both of carbon and nitrogen to form an implant region within the first semiconductor material; and
thermally treating the implant region to heal damage imparted during the implant.

13. The method of claim 1 wherein the heavily-doped region extends to a depth within the first semiconductor material of less than or equal to about 100 nanometers.

14. The method of claim 1 wherein the second semiconductor material is epitaxially grown to a thickness of at least about 2000Å.

15. The method of claim 1 wherein the second trenches are substantially orthogonal to the first trenches.

16. A method of forming a semiconductor construction, comprising:
forming a heavily-doped region within a first semiconductor material in an array region of a base, the array region having a planar upper surface that is recessed relative to uppermost surfaces of a peripheral region of the base;
epitaxially growing a second semiconductor material over the first semiconductor material;
patterning the second semiconductor material to form circuit components;
patterning the heavily-doped region to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another; and
at least some of the patterning of the heavily-doped region occurring simultaneously with at least some of the patterning of the second semiconductor material.

17. The method of claim 16 wherein the heavily-doped region is n-type.

18. The method of claim 16 wherein the heavily-doped region is p-type.

19. The method of claim 16 wherein the first semiconductor material is monocrystalline silicon.

20. The method of claim 16 wherein the first and second semiconductor materials are monocrystalline silicon.

21. The method of claim 16 further comprising in situ doping of the second semiconductor material during the epitaxial growth of the second semiconductor material.

22. The method of claim 16 wherein the circuit components are vertical transistors.

23. The method of claim 16 wherein the circuit components are BJTs.

24. The method of claim 16 wherein the circuit components are diodes.

Assignees

• Micron Technology Inc

Inventors

• Guha Jaydip
• Surthi Shyam

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/3458

  Monocrystalline · CPC title

• H10P14/3438

  Doping during depositing · CPC title