Protection devices for precision mixed-signal electronic circuits and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9362265-B2
Application number	US-201514593477-A
Country	US
Kind code	B2
Filing date	Jan 9, 2015
Priority date	Mar 19, 2012
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

First claim

What is claimed is:

1. A protection device for a mixed-signal integrated circuit, the protection device comprising:
a semiconductor substrate;
a first n-type well in the semiconductor substrate;
a first p-type well in the semiconductor substrate adjacent the first n-type well;
a first n-type active region disposed along a boundary of the first n-type well and the first p-type well;
a second n-type active region in the first p-type well;
a first p-type active region in the first n-type well;
a gate structure over the first n-type well, wherein the first p-type active region is disposed on a first side of the gate structure, and wherein the first n-type active region is disposed on a second side of the gate structure opposite the first side;
a second p-type well in the semiconductor substrate, wherein the first n-type well is positioned between the first p-type well and the second p-type well; and
an n-type isolation layer beneath the first p-type well, the first n-type well, and the second p-type well.

2. The protection device of claim 1 , further comprising a first pad electrically connected to the first p-type active region and a second pad electrically connected to the second n-type active region.

3. The protection device of claim 2 , wherein during a transient overvoltage stress event between the first pad and the second pad, a first conduction path is provided under the gate structure and a second conduction path is provided through gate coupling to decrease a turn-on response time and reduce a transient breakdown voltage between the first n-type well and the first p-type well during the transient overvoltage stress event.

4. The protection device of claim 3 , wherein the first gate structure comprises a p-type doped poly-crystalline gate region adjacent the first p-type active region and an n-type doped poly-crystalline gate region adjacent the first n-type active region.

5. The protection device of claim 1 , further comprising a second p-type active region disposed in the second p-type well, wherein the second p-type active region is electrically connected to the second n-type active region.

6. The protection device of claim 5 , further comprising a first pad electrically connected to the first p-type active region and a second pad electrically connected to the second n-type active region and to the second p-type active region.

7. The protection device of claim 1 , wherein the first n-type well is implemented as a first ring that surrounds and abuts the first p-type well.

8. The protection device of claim 7 , wherein the second p-type well is implemented as a second ring that surrounds and abuts the first n-type well.

9. The protection device of claim 8 , further comprising a second n-type well, wherein the second n-type well is implemented as a third ring that surrounds and abuts the second p-type well.

10. The protection device of claim 9 , further comprising a third p-type well, wherein the third p-type well is implemented as a fourth ring that surrounds, but does not abut, the second n-type well.

11. The protection device of claim 1 , further comprising a second n-type well, wherein the second p-type well is positioned between the first n-type well and the second n-type well, wherein the second n-type well is electrically connected to the first n-type well via the n-type isolation layer.

12. The protection device of claim 1 , wherein the first p-type well is electrically connected to the second p-type well.

13. An integrated circuit comprising:
a first pin;
a semiconductor substrate; and
a protection device comprising:
a first n-type well in the semiconductor substrate;
a first p-type well in the semiconductor substrate adjacent the first n-type well;
a first n-type active region disposed along a boundary of the first n-type well and the first p-type well;
a second n-type active region in the first p-type well;
a first p-type active region in the first n-type well and electrically connected to the first pin;
a gate structure over the first n-type well, wherein the first p-type active region is disposed on a first side of the gate structure, and wherein the first n-type active region is disposed on a second side of the gate structure opposite the first side;
a second p-type well in the semiconductor substrate, wherein the first n-type well is positioned between the first p-type well and the second p-type well; and
a means for isolating the protection device from the semiconductor substrate.

14. A method of making a protection device, the method comprising:
forming an n-type isolation layer in a semiconductor substrate;
forming a first n-type well in the semiconductor substrate over the n-type isolation layer;
forming a first p-type well in the semiconductor substrate adjacent the first n-type well and over the n-type isolation layer;
forming a second p-type well in the semiconductor substrate over the n-type isolation layer, wherein the first n-type well is positioned between the first p-type well and the second p-type well;
forming a gate structure over the first n-type well;
forming a first n-type active region along a boundary of the first n-type well and the first p-type well;
forming a second n-type active region in the first p-type well; and
forming a first p-type active region in the first n-type well, wherein the first p-type active region is disposed on a first side of the gate structure, and wherein the first n-type active region is disposed on a second side of the gate structure opposite the first side.

15. The method of claim 14 , further comprising forming a second p-type active region in the second p-type well, and electrically connecting the second p-type active region to the second n-type active region.

16. The method of claim 14 , further comprising electrically connecting the first p-type well to the second p-type well.

17. The method of claim 14 , wherein forming the first n-type well comprising forming a first ring that surrounds and abuts the first p-type well.

18. The method of claim 17 , wherein forming the second p-type well comprises forming a second ring that surrounds and abuts the first n-type well.

19. The method of claim 18 , further comprising forming a second n-type well as a third ring that surrounds and abuts the second p-type well.

20. The method of claim 19 , further comprising forming a third p-type well as a fourth ring that surrounds, but does not abut, the second n-type well.

Assignees

• Analog Devices Inc

Inventors

• Salcedo Javier Alejandro
• Parthasarathy Srivatsan

Classifications

• H10D89/711 Primary

  using bipolar transistors as protective elements · CPC title

• H10D84/0112

  Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D89/713 Primary

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H01L27/0259

  Electricity · mapped topic