Parameter extraction of DFT

Patent metadata

Field	Value
Publication number	US-9727675-B2
Application number	US-201615081735-A
Country	US
Kind code	B2
Filing date	Mar 25, 2016
Priority date	Sep 26, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.

First claim

The invention claimed is:

1. An EDA tool comprising:
a data processor;
storage configured to provide computer program instructions to the processor, including:
an intermediary interacting with a plurality of simulators to perform an EDA simulation at a plurality of different simulation scales, the plurality of simulators including:
a first set of one or more ab initio simulators at a first simulation scale; and
a second set of one of more non-ab initio simulators at a second simulation scale larger than the first simulation scale,

wherein the intermediary processes outputs of the first set of one or more ab initio simulators to generate a set of semiconductor material quantities received and processed by the second set of one or more non-ab initio simulators as values for input parameters, said quantities including at least one member of the group consisting of: an effective mass tensor, a non-parabolicity value, and N-band k.p model parameter values where N is an integer.

2. The EDA tool of claim 1 , wherein, the data processor is responsive to one or more of the input parameters to at least one of the second set of one of more non-ab initio simulators having an inaccuracy, such that the data processor automatically executes at least one of the first set of one or more simulators to provide results as values for said one or more of the input parameters to said at least one of the second set of one of more simulators, thereby lessening the inaccuracy.

3. The EDA tool of claim 1 , wherein the first set of one or more ab initio simulators includes a density functional theory simulator, and said second set of one or more non-ab initio simulators excludes the density functional theory simulator.

4. The EDA tool of claim 3 , wherein the intermediary causes the density functional theory simulator to perform with at least one of an internal field and a potential barrier, and without an external field.

5. The EDA tool of claim 3 , wherein the intermediary causes the density functional theory simulator to perform with an external field provided by the second set of one of more non-ab initio simulators.

6. The EDA tool of claim 1 , wherein the set of semiconductor material quantities includes the effective mass tensor.

7. The EDA tool of claim 1 , wherein the set of semiconductor material quantities includes the non-parabolicity.

8. The EDA tool of claim 1 , wherein the set of semiconductor material quantities includes the N-band k.p model parameter values.

9. The EDA tool of claim 1 , wherein the intermediary causes the first set of one or more ab initio simulators to simulate a first volume, the intermediary causes the second set of one or more non-ab initio simulators to simulate a second volume, the first volume being smaller than the second volume.

10. The EDA tool of claim 1 , wherein the intermediary causes an iterative process between the first set of one or more ab initio simulators and the second set of one of more non-ab initio simulator, the iterative process following simulation functionality feedback.

11. The EDA tool of claim 1 , wherein the intermediary causes an iterative process between the first set of one or more ab initio simulators and the second set of one of more non-ab initio simulator, the iterative process following calculation efficiency and precision feedback.

12. The EDA tool of claim 1 , wherein the intermediary causes an iterative process between the first set of one or more ab initio simulators and the second set of one of more non-ab initio simulator, the iterative process following iterative looped feedback.

13. A computer-implemented method comprising:
causing a plurality of simulators to perform an EDA simulation at a plurality of different simulation scales using a computer system, the plurality of simulators including:
a first set of one or more ab initio simulators at a first simulation scale; and
a second set of one of more non-ab initio simulators at a second simulation scale larger than the first simulation scale; and

processing outputs of the first set of one or more ab initio simulators to generate a set of semiconductor material quantities received and processed by the second set of one or more non-ab initio simulators as values for input parameters, said quantities including at least one member of the group consisting of: an effective mass tensor, a non-parabolicity value, and N-band k.p model parameter values where N is an integer.

14. The computer-implemented method of claim 13 , wherein, the computer system is responsive to one or more of the input parameters to at least one of the second set of one of more non-ab initio simulators having an inaccuracy, such that the computer system automatically executes at least one of the first set of one or more non-ab initio simulators to provide results as values for said one or more of the input parameters to said at least one of the second set of one of more non-ab initio simulators, thereby lessening the inaccuracy.

15. The computer-implemented method of claim 13 , wherein the first set of one or more ab initio simulators includes a density functional theory simulator, and said second set of one or more non-ab initio simulators excludes the density functional theory simulator.

16. The computer-implemented method of claim 15 , wherein the intermediary causes the density functional theory simulator to perform with at least one of an internal field and a potential barrier, and without an external field.

17. The computer-implemented method of claim 15 , wherein the intermediary causes the density functional theory simulator to perform with an external field provided by the second set of one of more non-ab initio simulators.

18. The computer-implemented method of claim 13 , wherein the set of semiconductor material quantities includes the effective mass tensor.

19. The computer-implemented method of claim 13 , wherein the set of semiconductor material quantities includes the non-parabolicity.

20. The computer-implemented method of claim 13 , wherein the set of semiconductor material quantities includes the N-band k.p model parameter values.

21. The computer-implemented method of claim 13 , wherein the intermediary causes the first set of one or more ab initio simulators to simulate a first volume, the intermediary causes the second set of one or more non-ab initio simulators to simulate a second volume, the first volume being smaller than the second volume.

22. The computer-implemented method of claim 13 , wherein the intermediary causes an iterative process between the first set of one or more ab initio simulators and the second set of one of more non-ab initio simulator, the iterative process following simulation functionality feedback.

23. The computer-implemented method of claim 13 , wherein the intermediary causes an iterative process between the first set of one or more ab initio simulators and the second set of one of more non-ab initio simulator, the iterative process following calculation efficiency and precision feedback.

24. The computer-implemented method of claim 13 , wherein the intermediary causes an iterative process between the first set of one or more ab initio simulators and the second set of one of more non-ab initio simulator, the iterative process following iterative looped feedback.

Assignees

• Synopsys Inc

Inventors

• Liu Jie
• Moroz Victor
• Shaughnessy-Culver Michael C
• Smith Stephen Lee
• Oh Yong-Seog
• Balasingam Pratheep
• Ma Terry Sylvan Kam-Chiu

Classifications

• G06F30/23

  using finite element methods [FEM] or finite difference methods [FDM] · CPC title

• G06F30/33 Primary

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F30/3312

  Timing analysis · CPC title