Breakdown voltage blocking device

Patent metadata

Field	Value
Publication number	US-9722041-B2
Application number	US-201213622997-A
Country	US
Kind code	B2
Filing date	Sep 19, 2012
Priority date	Sep 19, 2012
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

In one embodiment, a breakdown voltage blocking device can include an epitaxial region located above a substrate and a plurality of source trenches formed in the epitaxial region. Each source trench can include a dielectric layer surrounding a conductive region. The breakdown voltage blocking device can also include a contact region located in an upper surface of the epitaxial region along with a gate trench formed in the epitaxial region. The gate trench can include a dielectric layer that lines the sidewalls and bottom of the gate trench and a conductive region located between the dielectric layer. The breakdown voltage blocking device can include source metal located above the plurality of source trenches and the contact region. The breakdown voltage blocking device can include gate metal located above the gate trench.

First claim

What is claimed is:

1. A breakdown voltage blocking device comprising:
an epitaxial region located above a substrate;
a first trench and a second trench formed in said epitaxial region, each of said first and second trenches comprising a dielectric layer surrounding and covering a conductive region, a first mesa formed by said first and second trenches;
a first contact region located in an upper surface of said first mesa;
a second contact region located in an upper surface of said epitaxial region and located adjacent to said first trench;
a third trench formed in said epitaxial region, said third trench comprising a dielectric layer that lines the sidewalls and bottom of said third trench and a conductive region located between said dielectric layer, a second mesa formed by said second and third trenches, said second mesa is free of a contact region;
a dielectric layer formed over said second mesa and contacting said dielectric layer of said second trench and said dielectric layer of said third trench;
a first metal formed over said first and second trenches and said first and second contact regions; and
a second metal formed over said third trench.

2. The breakdown voltage blocking device of claim 1 , wherein said first and second contact regions comprise Schottky contacts.

3. The breakdown voltage blocking device of claim 1 , wherein said first and second contact regions comprise ohmic contacts.

4. The breakdown voltage blocking device of claim 1 , further comprising:
a p-n junction.

5. The breakdown voltage blocking device of claim 1 , further comprising:
a doped region located below said second contact region.

6. The breakdown voltage blocking device of claim 1 , wherein said substrate comprising an N+ type dopant, said epitaxial region comprising an N− type dopant, and said first and second contact regions each comprising an N+ type dopant.

7. The breakdown voltage blocking device of claim 1 , wherein said substrate comprising a P+ type dopant, said epitaxial region comprising a P− type dopant, and said first and second contact regions each comprising a P+ type dopant.

8. The breakdown voltage blocking device of claim 1 , wherein said third trench is wider than each of said first and second trenches.

9. The breakdown voltage blocking device of claim 1 , wherein said conductive region of said third trench is wider than each of said conductive region of said first and second trenches.

10. A circuit comprising:
a metal oxide semiconductor field effect transistor (MOSFET) device; and
a breakdown voltage blocking device coupled to said MOSFET device, said breakdown voltage blocking device comprising:
an epitaxial region located above a substrate;
a first trench and a second trench formed in said epitaxial region, each of said first and second trenches comprising a dielectric layer surrounding and formed over a conductive region, a first mesa formed by said first and second trenches;
a first contact region located in an upper surface of said first mesa;
a second contact region located in an upper surface of said epitaxial region and located adjacent to said first trench;
a third trench formed in said epitaxial region, said third trench comprising a dielectric layer that lines the sidewalls and bottom of said third trench and a conductive region located between said dielectric layer, a second mesa formed by said second and third trenches, said second mesa is free of a contact region;
a dielectric layer formed over said second mesa and contacting said dielectric layer of said second trench and said dielectric layer of said third trench;
a first metal formed over said first and second trenches and said first and second contact regions; and
a second metal formed over said third trench.

11. The circuit of claim 10 , wherein said breakdown voltage blocking device further comprising a terminal coupled to a source terminal of said MOSFET device.

12. The circuit of claim 10 , wherein said breakdown voltage blocking device further comprising a terminal coupled to a drain terminal of said MOSFET device.

13. The circuit of claim 10 , wherein said MOSFET device is a power MOSFET device.

14. The circuit of claim 10 , wherein said first and second contact regions comprise Schottky contacts.

15. The circuit of claim 10 , wherein said first and second contact regions comprise ohmic contacts.

16. The circuit of claim 10 , further comprising:
a p-n junction.

17. A breakdown voltage blocking device comprising:
an epitaxial region located above a substrate;
a first trench and a second trench formed in said epitaxial region, each of said first and second trenches comprising a dielectric layer encasing a conductive region, a first mesa formed by said first and second trenches;
a first contact region located in an upper surface of said first mesa;
a second contact region located in an upper surface of said epitaxial region and located adjacent to said first trench;
a third trench formed in said epitaxial region, said third trench comprising a dielectric layer that lines the sidewalls and bottom of said third trench and a conductive region located between said dielectric layer, a second mesa formed by said second and third trenches, said second mesa is free of a contact region;
a dielectric layer formed over said second mesa and contacting said dielectric layer of said second trench and said dielectric layer of said third trench;
a first metal formed over said first and second trenches and said first and second contact regions; and
a second metal formed over said third trench;
said breakdown voltage blocking device is operable to block more voltage the greater the depth of said first, second and third trenches.

18. The breakdown voltage blocking device of claim 17 , wherein the breakdown voltage blocking device blocks more voltage the greater the thickness of the dielectric layer of said first, second and third trenches.

19. The breakdown voltage blocking device of claim 17 , wherein the breakdown voltage blocking device blocks more voltage the greater the thickness of the epitaxial region located between the substrate and the bottom of said first, second and third trenches.

20. The breakdown voltage blocking device of claim 17 , wherein said conductive region of said third trench is wider than each of said conductive region of said first and second trenches.

Assignees

• Vishay Siliconix

Inventors

• Xu Robert Q
• Chen Qufei

Classifications

• H01L29/7839

  Electricity · mapped topic

• H01L29/7391

  Electricity · mapped topic

• H01L29/66143

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic