MOSFET active area and edge termination area charge balance

Patent metadata

Field	Value
Publication number	US-9484451-B2
Application number	US-20384608-A
Country	US
Kind code	B2
Filing date	Sep 3, 2008
Priority date	Oct 5, 2007
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.

First claim

We claim:

1. A method for fabricating a semiconductor device having an active area and an edge termination area, said method comprising:
forming a first plurality of localized implants in a first operation at the bottom of trenches located in said active area and at the bottom of trenches located in said edge termination area; and
forming a second plurality of localized implants in a second operation at the bottom of said trenches located in said active area while leaving alone said first plurality of implants located in said edge termination area, wherein said second plurality of implants formed at said bottom of said trenches located in said active area causes said implants formed at the bottom of said trenches located in said active area to reach a predetermined concentration,
wherein said first plurality of localized implants are formed before a masking of said edge termination area and said second plurality of implants are formed after a masking of said edge termination area.

2. The method of claim 1 further comprising:
masking said edge termination area before said forming said second plurality of implants at said bottom of said trenches located in said active area.

3. The method of claim 1 further comprising:
forming a layer of oxide on the walls of said trenches located in said active area; and
forming a layer of oxide on the walls of said trenches located in said edge termination area, wherein said layer of oxide on the walls of said trenches located in said edge termination area is thicker than the layer of oxide formed on the walls of said trenches located in said active area.

4. The method of claim 1 further comprising:
forming a plurality of edge termination contacts in said edge termination area.

5. The method of claim 3 wherein said forming a layer of oxide on the walls of said trenches located in said active area is performed after said forming a layer of oxide on the walls of said trenches located in said edge termination area.

6. The method of claim 1 wherein said first and said second plurality of implants result in a simultaneous charge balance within said active area and within said edge termination area.

7. The method of claim 1 wherein said first and said second plurality of implants are phosphorous implants for N-channel devices and boron implants for P-channel devices.

8. The method of claim 1 wherein said forming oxide on said walls of said trenches located in said active area and said trenches located in said edge termination area is implemented using a low thermal oxide (LTO) process.

9. A method for fabricating a MOSFET having an active area and an edge termination area, said method comprising:
forming first and second semiconductor layers on a substrate;
forming trenches in said active area and in said edge termination area in the topmost of said semiconductor layers;
forming first multiple localized implants at the bottom of said trenches formed in said active area and in said edge termination area;
masking said edge termination area;
forming second multiple localized implants at the bottom of said trenches formed in said active area; and
forming an oxide layer in said trenches formed in said edge termination area and forming an oxide layer in said trenches formed in said active area, wherein said oxide layer formed in said trenches in said edge termination area is thicker than said oxide layer formed in said trenches in said active area,
wherein said first plurality of localized implants are formed before a masking of said edge termination area and said second plurality of implants are formed after a masking of said edge termination area.

10. The method of claim 9 further comprising:
forming a polysilicon layer that fills said trenches and performing polysilicon doping and a polysilicon etch back of said polysilicon layer;
forming source implants and a threshold voltage adjustment implant;
forming planar and trench contacts; and
forming contact implants and a metallization layer in said contacts and a passivation layer on said metallization layer.

11. The method of claim 9 further comprising:
forming a plurality of edge termination contacts in said edge termination area.

12. The method of claim 9 wherein said forming said oxide layer in said trenches formed in said active area is performed after said forming said oxide layer in said trenches formed in said edge termination area.

13. The method of claim 9 wherein said first and said second plurality of implants results in a simultaneous charge balance within said active area and within said edge termination area.

14. The method of claim 9 wherein said first and said second plurality of implants are phosphorous implants for N-channel devices and boron implants for P-channel devices.

15. The method of claim 9 wherein said oxide layer formed in said trenches formed in said active area and formed in said trenches formed in said edge termination area is formed using a low thermal oxide (LTO) process.

Assignees

• Chen Qufei
• Terrill Kyle
• Shi Sharon
• Vishay Siliconix

Inventors

• Chen Qufei
• Terrill Kyle
• Shi Sharon

Classifications

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10D30/655

  having edge termination structures · CPC title

• H10D30/665

  having edge termination structures · CPC title