Circuits and methods providing mutual capacitance in vertical electrical connections

Patent metadata

Field	Value
Publication number	US-9722012-B1
Application number	US-201615255412-A
Country	US
Kind code	B1
Filing date	Sep 2, 2016
Priority date	Sep 2, 2016
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

An electrical device including a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer.

First claim

What is claimed is:

1. An electrical device comprising:
a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers;
a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the first vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer; and
a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer, wherein the first capacitive structure is in an elongated shape, wherein a length dimension of the first capacitive structure extends toward the second capacitive structure.

2. The electrical device of claim 1 , wherein the first dielectric layer is between the top layer and the bottom layer.

3. The electrical device of claim 1 , wherein the first capacitive structure and the second capacitive structure are disposed on the bottom layer.

4. The electrical device of claim 1 , wherein the second capacitive structure is also in the elongated shape, wherein a length dimension of the second capacitive structure extends toward the first capacitive structure.

5. The electrical device of claim 1 , wherein the structure having the plurality of dielectric layers comprises a semiconductor die package.

6. The electrical device of claim 1 , wherein the structure having a plurality of dielectric layers comprises a semiconductor die.

7. An electrical device comprising:
a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers;
a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the first vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer; and
a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer, wherein the structure having the plurality of dielectric layers comprises a Printed Circuit Board (PCB);
a plurality of socket pins in communication with a top surface of the PCB and in electrical communication with the first vertical electrical connection and the second vertical electrical connection;
a semiconductor die package disposed on top of the plurality of socket pins and having a first set of electrical contacts in electrical communication with the plurality of socket pins; and
a semiconductor die mounted to the semiconductor die package and having a second set of electrical contacts in electrical communication with the semiconductor die package.

8. A method comprising:
conducting an electrical signal in a first vertical electrical connection; and
during conducting the electrical signal, storing energy in an electrical field by mutual capacitance between the first vertical electrical connection and a second vertical electrical connection, wherein the first vertical electrical connection and the second vertical electrical connection are each implemented in a multi-layer dielectric structure, further wherein the first vertical electrical connection includes a first capacitive structure extending in a plane perpendicular to a vertical dimension of the first vertical electrical connection, further wherein the second vertical electrical connection includes a second capacitive structure extending in the plane, and wherein the first capacitive structure and second capacitive structure are located within a same layer of the multi-layer dielectric structure.

9. The method of claim 8 , wherein conducting an electrical signal comprises conducting the electrical signal to or from a memory device.

10. The method of claim 9 , wherein storing energy in the electric field by mutual capacitance comprises storing energy in an electrical field at least in part by the first capacitive structure and the second capacitive structure.

11. The method of claim 10 , wherein conducting the electrical signal in the first vertical electrical connection comprises:
conducting the electrical signal in a horizontal electrical trace from the first vertical electrical connection to a third vertical electrical connection in communication with the horizontal electrical trace, wherein the horizontal electrical trace is in a different layer of the multi-layer dielectric structure than the first capacitive structure and the second capacitive structure.

12. The method of claim 11 , wherein conducting the electrical signal in the first vertical electrical connection comprises:
conducting the electrical signal between layers of the multi-layer dielectric structure.

13. An apparatus comprising:
a structure having a plurality of dielectric layers;
first vertical means for conducting an electrical signal between ones of the dielectric layers including a first mutual capacitance structure that extends in a plane perpendicular to a vertical dimension of the first vertical means, wherein the first mutual capacitance structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below a top layer; and
second vertical means for conducting an electrical signal between ones of the dielectric layers including a second mutual capacitance structure extending in the plane and disposed on the first dielectric layer, wherein the first mutual capacitance structure comprises an elongated shape, wherein a length dimension of the first mutual capacitance structure extends toward the second mutual capacitance structure.

14. The apparatus of claim 13 , wherein the first mutual capacitance structure and the second mutual capacitance structure are disposed on a bottom layer of the plurality of dielectric layers.

15. The apparatus of claim 13 , wherein the structure having the plurality of dielectric layers comprises a semiconductor die package.

16. An apparatus comprising:
a structure having a plurality of dielectric layers;
first vertical means for conducting an electrical signal between ones of the dielectric layers including a first mutual capacitance structure that extends in a plane perpendicular to a vertical dimension of the first vertical means, wherein the first mutual capacitance structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below a top layer;
second vertical means for conducting an electrical signal between ones of the dielectric layers including a second mutual capacitance structure extending in the plane and disposed on the first dielectric layer, wherein the structure having the plurality of dielectric layers comprises a Printed Circuit Board (PCB);
a plurality of socket pins in communication with a top surface of the PCB and in electrical communication with the first vertical means and the second vertical means;
a semiconductor

Assignees

• Qualcomm Inc

Inventors

• Pathmanathan Priyatharshan
• Patel Devarshi
• Northgrave Dennis Allen
• Roberts Kyle

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• H05K1/0228 Primary

  Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors (balanced signal pairs H05K1/0245) · CPC title