Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
US9105635B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105635-B2 |
| Application number | US-201313801998-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2013 |
| Priority date | Mar 13, 2013 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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A metal surface feature, such as a pad, terminating a vertical transition through a substrate, such as an IC package substrate, includes one or more stubs providing high edge surface area to couple with one or more complementary stubs on an adjacent metal surface feature to provide a desired amount of mutual capacitance that may at least partially cancel crosstalk for an overall channel crosstalk (e.g., FEXT) reduction. In embodiments, capacitive coupling of adjacent pads is provided for more than two pads to achieve crosstalk reduction of more than one victim-aggressor pair and/or to achieve crosstalk reduction of more than two aggressors. In embodiments, the pads have a large pitch (e.g., 1000 μm) suitable for interfacing to an interposer or PCB socket, while the gap between the stubs is small (e.g., 15 μm), as limited only by the minimum spacing allowed for metal features on the opposite side of the package employed for interfacing to the IC.
Opening claim text (preview).
What is claimed is: 1. An integrated circuit (IC) package substrate, comprising: a first conductive vertical transition passing through a thickness of the substrate beginning at a first top-side metal feature on a first substrate side and ending at a first bottom-side metal feature on a second substrate side, opposite the first side, wherein the first bottom-side metal feature is a first signal I/O channel pad; and a second conductive vertical transition passing through the subs…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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