Online learning based algorithms to increase retention and reuse of GPU-generated dynamic surfaces in outer-level caches

Patent metadata

Field	Value
Publication number	US-9720829-B2
Application number	US-201113993811-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Some implementations disclosed herein provide techniques for caching memory data and for managing cache retention. Different cache retention policies may be applied to different cached data streams such as those of a graphics processing unit. Actual performance of the cache with respect to the data streams may be observed, and the cache retention policies may be varied based on the observed actual performance.

First claim

What is claimed is:

1. A processor, comprising:
a cache;
first logic to monitor a subset of locations of the cache to determine performance of the cache, the determined performance indicating a reuse factor and a consumption factor, the first logic further to assign an age to each inserted cached data item based on the reuse factor and the consumption factor; and
second logic to apply a retention policy to the cache, when it is necessary to make room for a new data item, to evict a cached data item selected from cached data items having the lowest age, and to vary the retention policy in response to the determined cache performance;
wherein the reuse factor comprises a ratio of a number of subsequent accesses to a cached data item divided by a number of initial accesses to the cached data item.

2. The processor of claim 1 , further comprising:
a plurality of processing components that are to share the cache, wherein the plurality of processing components are to be associated with respective data streams;
wherein the first logic is further to determine individual performances corresponding to the respective data streams; and
wherein the second logic is further to apply different retention policies to the respective data streams, based at least in part on the individual performances corresponding to the respective data streams.

3. The processor of claim 1 , further comprising a plurality of components that are to share the cache.

4. The processor of claim 1 , wherein the cache is to cache a plurality of data streams associated with a graphics processing pipeline.

5. The processor of claim 1 , wherein:
the cache is to cache a plurality of data streams; and
the second logic is further to apply different retention policies to different data streams.

6. The processor of claim 1 , wherein:
the cache is to cache a plurality of data streams; and
the second logic is further to apply different retention policies to different data streams and to vary of the retention policies in response to the determined cache performance.

7. The processor of claim 1 , wherein the consumption factor comprises a ratio of a number of first uses of cached data items by a consumer divided by a number of cached data items inserted by a producer.

8. The processor of claim 1 , wherein the determined performance indicates observed characteristics of a plurality of data streams.

9. A system, comprising:
a cache having locations to store data in accordance with one or more retention policies;
first logic to monitor a subset of locations of the cache to determine performance of at least the subset of the cache locations, the determined performance indicating a reuse factor and a consumption factor, the first logic further to assign to each inserted cached data item an age based on the reuse factor and the consumption factor; and
second logic to apply a retention policy to the cache, when it is necessary to make room for a new data item, to evict a cached data item selected from cached data items having the lowest age, and to vary the one or more retention policies in response to the determined performance;
wherein the consumption factor comprises a ratio of a number of first uses of cached data items by a consumer divided by a number of cached data items inserted by a producer.

10. The system of claim 9 , further comprising:
a plurality of processor cores; and
a graphics processing unit;
wherein the processor cores and the graphics processing unit are to share the cache.

11. The system of claim 9 , further comprising a graphics processing pipeline having processing components that are to share the cache.

12. The system of claim 9 , further comprising:
a plurality of processing components that are to share the cache, wherein the plurality of processing components are to be associated with respective data streams; and
wherein the first logic is further to determine cache performances corresponding to the respective data streams.

13. The system of claim 9 , wherein:
the cache is to cache a plurality of data streams; and
the one or more retention policies correspond respectively to the data streams.

14. The system of claim 9 , wherein:
the cache is to cache a plurality of data streams; and
the second logic is to vary at least two of the retention policies in response to the determined performance.

15. The system of claim 9 , wherein the reuse factor comprises a ratio of a number of subsequent accesses to a cached data item divided by a number of initial accesses to the cached data item.

16. A method, comprising:
retaining elements of a cache in accordance with a cache retention policy;
observing performance of the cache by monitoring a subset of locations of the cache to;
determining performance of at least the subset of locations to generate a reuse factor and a consumption factor, and to assign to each inserted cached data item an age based on the reuse factor and the consumption factor;
applying a retention policy to the cache, when it is necessary to make room for a new data item, to evict a cached data item selected from cached data items having the lowest age; and
varying the cache retention policy in accordance with the observed performance of the cache
wherein the consumption factor comprises a ratio of a number of first uses of cached data items by a consumer divided by a number of cached data items inserted by a producer.

17. The method of claim 16 , wherein the subset of locations is fewer than all of the cache locations and distributed over the cache to enhance statistical validity of observations with respect to various data streams stored in the cache.

18. The method of claim 16 , wherein the observing is performed separately with respect to different data streams.

19. The method of claim 16 , further comprising applying different cache retention policies to different data streams.

20. The method of claim 16 , wherein the reuse factor comprises a ratio of a number of subsequent accesses to a cached data item divided by a number of initial accesses to the cached data item.

Assignees

• Srinivasan Suresh
• Ramesh Rakesh
• Subramoney Sreenivas
• Gaur Jayesh
• Intel Corp

Inventors

• Srinivasan Suresh
• Ramesh Rakesh
• Subramoney Sreenivas
• Gaur Jayesh

Classifications

• G06F12/0888 Primary

  using selective caching, e.g. bypass · CPC title

• G06T1/60

  Memory management · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title