CMOS ultrasonic transducers and related apparatus and methods

Patent metadata

Field	Value
Publication number	US-9718098-B2
Application number	US-201615158968-A
Country	US
Kind code	B2
Filing date	May 19, 2016
Priority date	Feb 5, 2013
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

CMOS Ultrasonic Transducers and processes for making such devices are described. The processes may include forming cavities on a first wafer and bonding the first wafer to a second wafer. The second wafer may be processed to form a membrane for the cavities. Electrical access to the cavities may be provided.

First claim

What is claimed is:

1. A method, comprising:
forming a cavity in a first wafer above a complementary metal oxide semiconductor (CMOS) circuit in the first wafer by etching the cavity to an etch stop, the first wafer including a metal electrode structure disposed within an insulating layer of the first wafer, wherein forming the cavity comprises etching an upper surface down to at least a level of the insulating layer of the first wafer in which the electrode structure is disposed;
directly bonding the first wafer and a second wafer to seal the cavity of the first wafer with the second wafer to form a sealed cavity, the second wafer including one or more of a silicon-on-insulator (SOI) wafer or a bulk silicon wafer having a degeneratively doped layer; and
forming an ultrasonic transducer membrane from the second wafer;
wherein the etch stop comprises the metal electrode structure.

2. The method of claim 1 , further comprising forming an oxide layer on the etched first wafer prior to the bonding such that the bonding results in a silicon-to-oxide bond between the first and second wafers.

3. A method, comprising:
forming a cavity in a first wafer above a complementary metal oxide semiconductor (CMOS) circuit in the first wafer by etching the cavity to an etch stop, the first wafer including a metal electrode structure disposed within an insulating layer of the first wafer, wherein forming the cavity comprises etching an upper surface down to at least a level of the insulating layer of the first wafer in which the electrode structure is disposed;
forming a conductive layer on the insulating layer of the first wafer, wherein forming the cavity comprises etching the conductive layer to the insulating layer such that insulating layer serves as the etch stop;
directly bonding the first wafer and a second wafer to seal the cavity of the first wafer with the second wafer to form a sealed cavity, the second wafer including one or more of a silicon-on-insulator (SOI) wafer or a bulk silicon wafer having a degeneratively doped layer; and
forming an ultrasonic transducer membrane from the second wafer.

4. The method of claim 3 , wherein the conductive layer is a doped silicon layer.

5. The method of claim 4 , wherein the bonding results in a silicon-to-silicon bond between the first and second wafers.

6. The method of claim 3 , wherein the conductive layer is a metal layer.

7. The method of claim 6 , further comprising forming a metal layer on the second wafer prior to the bonding such that the bonding results in a metal-to-metal bond between the first and second wafers.

Assignees

• Butterfly Network Inc

Inventors

• Rothberg Jonathan M
• Fife Keith G
• Ralston Tyler S
• Charvat Gregory L
• Sanchez Nevada J

Classifications

• B81B7/0077

  Other packages not provided for in groups B81B7/0035 - B81B7/0074 · CPC title

• B81B2207/015

  the micromechanical device and the control or processing electronics being integrated on the same substrate · CPC title

• B06B1/0292 Primary

  Electrostatic transducers, e.g. electret-type · CPC title

• B81B3/0021

  Transducers for transforming electrical into mechanical energy or vice versa (dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00) · CPC title

• B06B1/02 Primary

  making use of electrical energy (B06B1/18, B06B1/20 take precedence) · CPC title