Microfabricated ultrasonic transducers and related apparatus and methods

Patent metadata

Field	Value
Publication number	US-2016009544-A1
Application number	US-201514799484-A
Country	US
Kind code	A1
Filing date	Jul 14, 2015
Priority date	Mar 2, 2015
Publication date	Jan 14, 2016
Grant date	—

Abstract

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

First claim

What is claimed is:

1 . A method of bonding an engineered substrate having first and second wafers bonded together, the first wafer having an isolation trench isolating an electrode region of the first wafer, the method comprising:
forming a redistribution layer on an integrated circuit (IC) wafer having an IC; forming a solder bump array on the redistribution layer; and solder bump bonding the engineered substrate with the IC wafer such that the first wafer of the engineered substrate is between the IC wafer and the second wafer of the engineered substrate, wherein a first solder bump of the solder bump array electrically contacts the electrode region of the first wafer.

2 . The method of claim 1 , wherein the first wafer includes a first side proximate the second wafer and a second side distal the second wafer, and wherein the method further comprises, prior to solder bump bonding the engineered substrate with the IC wafer, forming a redistribution layer on the second side of the first wafer.

3 . The method of claim 1 , wherein the engineered substrate comprises a plurality of cavities in the first wafer or second wafer, wherein a first cavity of the plurality of cavities is aligned with the electrode region.

4 . The method of claim 1 , wherein solder bump bonding the engineered substrate with the IC wafer is performed in a wafer-scale packaging foundry.

5 . The method of claim 1 , further comprising dicing the engineered substrate and IC wafer subsequent to solder bump bonding the engineered substrate with the IC wafer.

6 . The method of claim 1 , wherein the first wafer of the engineered substrate has a thickness between approximately 200 microns and approximately 500 microns, and wherein the first wafer is not thinned prior to the solder bump bonding.

7 . The method of claim 1 , wherein the first wafer of the engineered substrate has a thickness between approximately 5 microns and approximately 200 microns.

8 . The method of claim 1 , further comprising electrically coupling the IC to the second wafer of the engineered substrate.

9 . An apparatus, comprising:
an engineered substrate including first and second substrates bonded together, wherein the first substrate has an isolation trench defining an electrode region; an integrated circuit (IC) substrate, having an IC, bonded with the first substrate of the engineered substrate and including a redistribution layer; and a solder bump array on the redistribution layer and forming a solder bump bond between the first substrate and the IC substrate, wherein a first solder bump of the solder bump array electrically contacts the electrode region.

10 . The apparatus of claim 9 , wherein the first substrate includes a first side proximate the second substrate and a second side distal the second substrate, and wherein the apparatus further comprises a redistribution layer on the second side of the first substrate.

11 . The apparatus of claim 9 , wherein the engineered substrate comprises a plurality of sealed cavities.

12 . The apparatus of claim 11 , wherein a first cavity of the plurality of cavities is aligned with the electrode region.

13 . The apparatus of claim 9 , wherein the first substrate of the engineered substrate has a thickness between approximate 200 microns and approximately 500 microns.

14 . The apparatus of claim 9 , wherein the first substrate of the engineered substrate has a thickness between approximately 5 microns and approximately 200 microns.

15 . The apparatus of claim 9 , further comprising an electrical path coupling the IC to the second substrate of the engineered substrate.

Assignees

• Butterfly Network Inc

Inventors

• Rothberg Jonathan M
• Alie Susan A
• Fife Keith G
• Sanchez Nevada J
• Ralston Tyler S

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/865

  Die-attach connectors and bond wires · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title