Complementary metal oxide semiconductor (CMOS) ultrasonic transducers and methods for forming the same

Patent metadata

Field	Value
Publication number	US-9242275-B2
Application number	US-201414208351-A
Country	US
Kind code	B2
Filing date	Mar 13, 2014
Priority date	Mar 15, 2013
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

Complementary metal oxide semiconductor (CMOS) ultrasonic transducers (CUTs) and methods for forming CUTs are described. The CUTs may include monolithically integrated ultrasonic transducers and integrated circuits for operating in connection with the transducers. The CUTs may be used in ultrasound devices such as ultrasound imaging devices and/or high intensity focused ultrasound (HIFU) devices.

First claim

What is claimed is:

1. An apparatus, comprising:
a semiconductor wafer having a complementary metal oxide semiconductor (CMOS) integrated circuit;
an electrode;
an insulating material having a cavity formed at least partially therein;
a conductive layer contacting the insulating material, sealing the cavity and having a first side proximate the cavity and a second side distal the cavity, wherein the electrode, cavity, and conductive layer together define, at least in part, an ultrasonic transducer, with the cavity being between the electrode and the conductive layer;
a conductive contact coupling the electrode to the CMOS integrated circuit; and
a conductive plug embedded in the insulating material and terminating on the first side of the conductive layer proximate the cavity without extending through the conductive layer such that a surface of the conductive plug is bonded with the first side of the conductive layer, wherein the conductive plug electrically connects the conductive layer to the CMOS integrated circuit, and
wherein the electrode and the conductive plug are electrically isolated from each other.

2. The apparatus of claim 1 , wherein the conductive layer represents a first layer of a membrane of the ultrasonic transducer.

3. The apparatus of claim 1 , wherein the conductive plug and the conductive layer are formed of a same material.

4. The apparatus of claim 1 , wherein the cavity has a first width, and wherein the electrode has a second width smaller than the first width.

5. The apparatus of claim 1 , wherein the cavity has a first width, and wherein the electrode has a second width larger than the first width.

6. The apparatus of claim 1 , wherein the conductive layer represents a coating layer on a silicon wafer.

7. The apparatus of claim 1 , further comprising a membrane stop coupled to the electrode.

8. The apparatus of claim 1 , wherein the conductive layer has a thickness less than five microns.

Assignees

• Butterfly Network Inc
• Butterfly Networks Inc

Inventors

• Rothberg Jonathan M
• Fife Keith G
• Ralston Tyler S
• Charvat Gregory L
• Sanchez Nevada J

Classifications

• G01N29/2406

  Electrostatic or capacitive probes, e.g. electret or cMUT-probes · CPC title

• B81C2203/0735

  Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit · CPC title

• B81B7/007

  Interconnections between the MEMS and external electrical signals · CPC title

• H04R19/005

  using semiconductor materials · CPC title

• B06B1/02

  making use of electrical energy (B06B1/18, B06B1/20 take precedence) · CPC title