Open solder mask and or dielectric to increase lid or ring thickness and contact area to improve package coplanarity

Patent metadata

Field	Value
Publication number	US-9716051-B2
Application number	US-201213668077-A
Country	US
Kind code	B2
Filing date	Nov 2, 2012
Priority date	Nov 2, 2012
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.

First claim

We claim:

1. A packaging substrate comprising:
a packaging structure having a chip mounting surface and a bottom surface, the packaging structure having at a plurality of conductive paths formed between the chip mounting surface and the bottom surface, the conductive paths providing electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface, the packaging structure having an opening formed in the chip mounting surface proximate a perimeter of the packaging structure; and
a stiffening microstructure disposed in the opening and coupled to the packaging structure.

2. The packaging substrate of claim 1 , wherein the stiffening microstructure is bonded to a bottom surface of the opening.

3. The packaging substrate of claim 1 , wherein the stiffening microstructure is bonded to a sidewall of the opening.

4. The packaging substrate of claim 1 , wherein the stiffening microstructure extends above the chip mounting surface.

5. The packaging substrate of claim 1 , wherein the chip mounting surface is on a solder mask layer, and the opening extends through the solder mask layer.

6. The packaging substrate of claim 5 , wherein the packaging structure further comprises:
a core layer disposed below the solder mask layer, the opening exposing a portion of the core layer.

7. The packaging substrate of claim 1 further comprising:
an integrated circuit chip mounted on the chip mounting surface.

8. The packaging substrate of claim 7 , wherein the stiffening microstructure includes a lid.

9. The packaging substrate of claim 8 further comprising:
a heat transfer medium providing a thermally conductive pathway between the lid and the integrated circuit chip.

10. The packaging substrate of claim 1 , wherein the stiffening microstructure is a ring.

11. The packaging substrate of claim 1 , wherein the packaging structure further comprises:
a ground reference plane layer disposed between the chip mounting surface and the bottom surface of the packaging structure, wherein the ground reference plane layer is in contact with the stiffening microstructure.

12. The packaging substrate of claim 1 further comprising a dielectric bonding agent coupling the stiffening microstructure to the packaging structure.

13. The packaging substrate of claim 1 further comprising a conductive bonding agent coupling the stiffening microstructure to the packaging structure.

14. A computing device, comprising:
a memory; and
a packaged semiconductor device communicatively coupled to the memory, wherein the packaged semiconductor device comprises:
a packaging structure having a chip mounting surface and a bottom surface, the packaging structure having an opening formed in the chip mounting surface proximate a perimeter of the packaging structure;
an integrated circuit chip disposed on the chip mounting surface and communicatively coupled to the memory though the packaging structure; and
a stiffening microstructure disposed in the opening and coupled to the packaging structure.

15. The packaging substrate of claim 14 , wherein the stiffening microstructure is bonded to at least one of a bottom surface and a sidewall of the opening.

16. The packaging substrate of claim 14 , wherein the stiffening microstructure extends above the chip mounting surface.

17. The packaging substrate of claim 14 , wherein the chip mounting surface is on a solder mask layer, and the opening extends through the solder mask layer.

18. The packaging substrate of claim 17 , wherein the packaging structure further comprises:
a core layer disposed below the solder mask layer, the opening exposing a portion of the core layer.

19. The packaging substrate of claim 14 , wherein the stiffening microstructure is one of a ring or a lid.

20. The packaging substrate of claim 14 , wherein the packaging structure further comprises:
a ground reference plane layer disposed between the chip mounting surface and the bottom surface of the packaging structure, wherein the stiffening microstructure is in contact with ground reference plane layer.

Assignees

• Nvidia Corp

Inventors

• Zhang Leilei
• Boja Ron
• Yee Abraham
• Bokharey Zuhair

Classifications

• H05K2201/09136

  Means for correcting warpage · CPC title

• H05K1/0271

  Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K2201/2009

  Reinforced areas, e.g. for a specific part of a flexible printed circuit · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title