Memristive devices with layered junctions and methods for fabricating the same
US-2015380464-A1 · Dec 31, 2015 · US
Memory cells having a number of conductive diffusion barrier materials and manufacturing methods
US9711717B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9711717-B2 |
| Application number | US-201514824128-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 12, 2015 |
| Priority date | Jul 26, 2013 |
| Publication date | Jul 18, 2017 |
| Grant date | Jul 18, 2017 |
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Abstract
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Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the select device and a second portion of the select device. Manufacturing methods are also described.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a memory cell, the method comprising: forming a number of select device materials and a number of memory element materials between a first electrode and a second electrode; interleaving a number of conductive diffusion barrier materials with at least one of: the number of select device materials; and the number of memory element materials; and separating a first of the number of conductive diffusion barrier materials from a second of the number of conductive diffusion barrier materials by at least one of a second select device material and a second memory element material. 2. The method of claim 1 , wherein each of the number of conductive diffusion barrier materials have a thickness in a range from 1 angstrom to 50 angstroms. 3. The method of claim 1 , wherein the number of conductive diffusion barrier materials comprises carbon, carbon nitride, or a combination thereof. 4. The method of claim 1 , wherein interleaving the number of conductive diffusion barrier materials comprises interleaving the number of conductive diffusion barrier materials with the number of select device materials to form a select device. 5. The method of claim 4 , wherein the number of select device materials form an ovonic threshold switch. 6. The method of claim 1 , wherein interleaving the number of conductive diffusion barrier materials comprises interleaving the number of conductive diffusion barrier materials with the number of memory element materials to form a programmable memory device. 7. The method of claim 1 , wherein a first portion of the number of conductive diffusion barrier materials have a first thickness and a second portion of the number of conductive diffusion barrier materials have a second thickness that is different than the first thickness. 8. The method of claim 1 , wherein each the number of conductive diffusion barrier materials have a different thickness. 9. The method of claim 1 , wherein each the number of conductive diffusion barrier materials have a same thickness. 10. The method of claim 1 , wherein the number of memory elements comprises a chalcogenide material. 11. The method of claim 1 , wherein each of the number of conductive diffusion barrier materials is parallel to the first electrode and the second electrode.
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H01L45/12Primary
Electricity · mapped topic
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- What does patent US9711717B2 cover?
- Memory cells having a select device material located between a first electrode and a second electrode, a memory element located between the second electrode and a third electrode, and a number of conductive diffusion barrier materials located between a first portion of the memory element and a second portion of the memory element. Memory cells having a select device comprising a select device m…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification H01L45/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).