Method for fabricating three-dimensional semiconductor device using buried stop layer in substrate
US-2024268119-A1 · Aug 8, 2024 · US
Surface treatment to improve resistive-switching characteristics
US9178149B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9178149-B2 |
| Application number | US-201414325015-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 7, 2014 |
| Priority date | May 1, 2008 |
| Publication date | Nov 3, 2015 |
| Grant date | Nov 3, 2015 |
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Abstract
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This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
First claim
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What is claimed is: 1. A method for fabricating a resistive memory device, the method comprising: providing a substrate, wherein the substrate comprises a first layer, the first layer operable as a first electrode; forming a second layer over the first layer, the second layer operable as a semiconductor layer; performing a surface treatment of the second layer, wherein the surface treatment comprises ion bombardment of a surface of the second layer, wherein the surfac…
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Frequently asked questions
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- What does patent US9178149B2 cover?
- This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching mem…
- Who is the assignee on this patent?
- Intermolecular Inc, Intermolecular Inc
- What technology area does this patent fall under?
- Primary CPC classification H10P30/20. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 03 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).