Methods of forming group III-nitride semiconductor devices including implanting ions directly into source and drain regions and annealing to activate the implanted ions

Patent metadata

Field	Value
Publication number	US-9711633-B2
Application number	US-11824308-A
Country	US
Kind code	B2
Filing date	May 9, 2008
Priority date	May 9, 2008
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Methods of forming a semiconductor device include forming a dielectric layer on a Group III-nitride semiconductor layer, selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer, implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions, and forming metal contacts on the source and drain regions of the semiconductor layer.

First claim

That which is claimed is:

1. A method of forming a semiconductor device, comprising:
providing a dielectric layer on a Group III-nitride semiconductor layer;
selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer;
implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer wherein an implantation energy is selected to provide a peak implant concentration near a two dimensional electron gas region at an interface of the semiconductor layer and a channel layer underlying the semiconductor layer, wherein the ions are implanted at an implant energy less than about 80 keV;
after selectively removing the portions of the dielectric layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions; and
providing metal contacts on the source and drain regions of the semiconductor layer,
wherein the peak implant concentration is within about 100 Å of the interface of the semiconductor layer and the channel layer.

2. The method of claim 1 , wherein the ions are implanted at a dose of about 8×10 14 ions/cm 2 to about 1×10 16 ions/cm 2 .

3. The method of claim 1 , wherein the peak implant concentration is greater than about 1×10 20 cm −3 .

4. The method of claim 3 , wherein the peak implant concentration is greater than about 3×10 20 cm −3 .

5. The method of claim 1 , wherein forming the metal contacts comprises:
providing a mask over the dielectric layer and the source and drain regions;
selectively removing portions of the mask to expose respective source and drain contact regions of the source and drain regions;
depositing a metal on the source and drain contact regions; and
removing the mask.

6. The method of claim 5 , wherein the source and drain contact regions are spaced apart from the dielectric layer by about 0.1 to 1 μm.

7. The method of claim 1 , wherein the dielectric layer comprises a first dielectric layer, the method further comprising:
forming a second dielectric layer over the first dielectric layer after implanting the source and drain regions; and
selectively removing portions of the second dielectric layer in the source and drain regions to expose respective source and drain contact regions in the source and drain regions.

8. The method of claim 7 , further comprising forming source and drain contacts in the source and drain contact regions, wherein the source and drain contacts are in direct contact with the second dielectric layer.

9. The method of claim 7 , further comprising forming source and drain contacts in the source and drain contact regions, wherein the source and drain contacts are spaced apart from the second dielectric layer by about 0.1 to about 1 μm.

10. The method of claim 1 , further comprising annealing the source and drain contacts at a temperature of about 450° C. to about 700° C.

11. The method of claim 1 , wherein the dielectric layer comprises SiN.

12. The method of claim 11 wherein annealing the semiconductor layer and the dielectric layer comprises annealing in an atmosphere containing NH 3 .

13. The method of claim 11 , wherein annealing the semiconductor layer and the dielectric layer comprises annealing at a temperature of from about 1000° C. to about 1300° C.

14. The method of claim 11 , wherein annealing the semiconductor layer and the dielectric layer comprises annealing in NH 3 and SiH 4 so that SiN is formed on the dielectric layer during the anneal.

15. The method of claim 11 , wherein forming the dielectric layer comprises forming the dielectric layer using LPCVD or MOCVD at a temperature greater than about 700° C.

16. The method of claim 15 , wherein forming the dielectric layer comprises forming the dielectric layer at a temperature of about 900° C. to about 1000° C.

17. The method of claim 1 , wherein the dielectric layer comprises a first dielectric layer, the method further comprising:
removing the first dielectric layer;
providing a second dielectric layer on the semiconductor layer;
selectively removing portions of the second dielectric layer over spaced apart source and drain contact regions of the semiconductor layer; and
forming metal contacts on the source and drain contact regions of the semiconductor layer.

18. The method of claim 17 , wherein the source and drain contacts are spaced apart from the second dielectric layer by about 0.1 to 1 μm.

19. The method of claim 17 , wherein the second dielectric layer comprises SiN.

20. The method of claim 17 , wherein the ions are implanted at an implant energy less than about 80 keV and a dose of about 8×10 14 ions/cm 2 to about 1×10 16 ions/cm 2 .

21. The method of claim 17 , wherein forming the metal contacts comprises:
providing a mask over the second dielectric layer and the source and drain regions;
selectively removing portions of the mask to expose the source and drain contact regions;
depositing a metal on the source and drain contact regions; and
removing the mask.

22. The method of claim 1 , wherein removing the portions of the dielectric layer provides a remaining portion of the dielectric layer that exposes portions of the source and drain regions of the semiconductor layer, and
wherein annealing the semiconductor layer and the dielectric layer comprises annealing the remaining portion of the dielectric layer and the exposed portions of the source and drain regions of the semiconductor layer.

23. The method of claim 1 , wherein implanting ions in the semiconductor layer comprises implanting ions at an angle to reduce channeling of the implanted ions.

24. The method of claim 23 , wherein the angle is about 7 degrees.

Assignees

• Sheppard Scott T
• Smith R Peter
• Wu Yifeng
• Heikman Sten
• Jacob-Mitos Matthew
• Cree Inc

Inventors

• Sheppard Scott T
• Smith R Peter
• Wu Yifeng
• Heikman Sten
• Jacob-Mitos Matthew

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title

• H01L29/66462

  Electricity · mapped topic

• H01L23/291

  Electricity · mapped topic