Semiconductor chip with anti-reverse engineering function

Patent metadata

Field	Value
Publication number	US-9711464-B2
Application number	US-201514862700-A
Country	US
Kind code	B2
Filing date	Sep 23, 2015
Priority date	Sep 23, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

First claim

What is claimed is:

1. An anti-reverse engineering semiconductor structure, comprising:
a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, said first wiring level closest to said semiconductor substrate and said last wiring level furthest from said semiconductor substrate, said stack of wiring levels including an intermediate wiring level between said first wiring level and said last wiring level;
active devices contained in said semiconductor substrate and said first wiring level, each wiring level of said stack of wiring levels comprising a dielectric layer containing electrically conductive wire;
a trench extending from said intermediate wiring level, through said first wiring level into said semiconductor substrate;
a liner on sidewalls and a bottom of said trench such that said trench comprises an open space;
a cap sealing a top of said open space of said trench, wherein each of said liner and said cap is configured to be damaged during a reverse engineering process such that said trench is exposed to said at least one wiring level of said stack of wiring levels; and
a chemical agent filling said open space of said trench, wherein said liner and said cap are chemically inert to said chemical agent, wherein portions of said at least one wiring level of said stack of wiring levels are not chemically inert to said chemical agent or a reaction product of said chemical agent, and wherein upon said liner or said cap being damaged during said reverse engineering process, said chemical agent is configured to damage wires, dielectric layers, dielectric materials, and said active devices of said at least one wiring level of said stack of wiring levels.

2. The structure of claim 1 , wherein said trench does not extend completely through said semiconductor substrate.

3. The structure of claim 1 , wherein said trench does not extend into said last wiring level.

4. The structure of claim 1 , wherein said chemical agent can chemically attack said wires, said dielectric layers or both said wires and said dielectric materials of said at least one wiring level of said stack of wiring levels.

5. The structure of claim 1 , wherein said chemical agent generates a second chemical agent that can chemically attack said wires, said dielectric layers or both said wires and said dielectric materials of said at least one wiring level of said stack of wiring levels when said chemical agent is exposed to air, oxygen or water.

6. An anti-reverse engineering semiconductor structure, comprising:
a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, said first wiring level closest to said semiconductor substrate and said last wiring level furthest from said semiconductor substrate, said stack of wiring levels including an intermediate wiring level between said first wiring level and said last wiring level;
active devices contained in said semiconductor substrate and said first wiring level, each wiring level of said stack of wiring levels comprising a dielectric layer containing electrically conductive wire;
a first trench extending from said intermediate wiring level, through said first wiring level into said semiconductor substrate;
a first liner on sidewalls and a bottom of said first trench such that said first trench comprises an open space;
a first cap sealing a top of said open space of said first trench, wherein each of said first liner and said first cap is configured to be damaged during a reverse engineering process such that said open space of said first trench is exposed to said at least one wiring level of said stack of wiring levels;
a second trench extending from said intermediate wiring level, through said first wiring level into said semiconductor substrate;
a second liner on sidewalls and a bottom of said second trench such that said second trench comprises an open space;
a second cap sealing a top of said open space of said second trench, wherein each of said second liner and said second cap is configured to be damaged during said reverse engineering process such that open space of said second trench is exposed to said at least one wiring level of said stack of wiring levels; and
a first chemical agent filling said first trench and a second chemical agent filling said second trench, wherein said first liner and said first cap are chemically inert to said first chemical agent, wherein said second liner and said second cap are chemically inert to said second chemical agent, wherein portions of said at least one wiring level of said stack of wiring levels are not chemically inert to a reaction product of said first chemical agent and said second chemical agent or can be physically damaged by said reaction product, and wherein upon said first liner or said first cap and said second liner or said second cap being damaged during said reverse engineering process, said reaction product is configured to damage wires, dielectric layers, dielectric materials, and said active devices of said at least one wiring level of said stack of wiring levels.

7. The structure of claim 6 , wherein said first trench and said trench do not extend completely through said semiconductor substrate.

8. The structure of claim 6 , wherein said first trench and said second trench do not extend into said last wiring level.

9. The structure of claim 6 , wherein said reaction product chemically attack said wires, said dielectric layers or both said wires and said dielectric materials of said at least one wiring level of said stack of wiring levels.

10. The structure of claim 6 , wherein first chemical agent and said second chemical agent generates heat when mixed.

11. The structure of claim 6 , wherein said mixture of first chemical agent and said second chemical agent generates a material that expands in volume.

12. The structure of claim 6 , wherein said first trench is proximate to said second trench and said first trench is separated from said second trench by regions of dielectric layers that said first and second trench extend through.

13. The structure of claim 6 , wherein said first trench and said second trench are coaxially aligned, said first trench inside of said second trench, said first trench separated from said second trench by regions of dielectric layers that said first and second trench extend through.

Assignees

• IBM

Inventors

• Cooney Iii Edward C
• Chen Fen
• Pratt Jonathan M
• Ritter Jason P
• Spinney Patrick S
• Tilley Anna

Classifications

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W42/40 Primary

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H01L21/76895

  Electricity · mapped topic