Test structure for electron beam inspection and method for defect determination using electron beam inspection

Patent metadata

Field	Value
Publication number	US-9711326-B1
Application number	US-201615001249-A
Country	US
Kind code	B1
Filing date	Jan 20, 2016
Priority date	Jan 20, 2016
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A test structure for electron beam inspection and a method for defect determination using electron beam inspection are provided. The test structure for electron beam inspection includes a semiconductor substrate, at least two conductive regions disposed on the semiconductor substrate, a connection structure disposed on the two conductive regions, and a cap dielectric layer disposed on the connection structure. The method for defect determination using the electron beam inspection includes the following steps. An electron beam inspection is preformed to a test structure with an instant detector and a lock-in amplifier. Signals received by the detector within a period of time are amplified by the lock-in amplifier. A defect in the test structure is determined by monitoring the signals received by the detector and amplified by the lock-in amplifier. The inspection accuracy is improved by the test structure and the method for defect determination in the present invention.

First claim

What is claimed is:

1. A test structure for electron beam inspection, comprising:
a semiconductor substrate;
at least two conductive regions disposed on the semiconductor substrate;
a connection structure disposed on the two conductive regions; and
a cap dielectric layer disposed on the connection structure.

2. The test structure for electron beam inspection according to claim 1 , wherein each of the two conductive regions comprises a doped region on a fin structure.

3. The test structure for electron beam inspection according to claim 2 , wherein each of the two conductive regions further comprises a metal silicide disposed on the doped region.

4. The test structure for electron beam inspection according to claim 1 , wherein the connection structure is a slot contact disposed in a dielectric layer.

Assignees

• United Microelectronics Corp

Inventors

• Lin Kuan-Chun
• Chou Chih-Chieh
• Chen Shih-Cheng
• Hung Chung-Chih
• Tsai Yung-Teng
• Chan Chi-Hung

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H01J2237/24495

  Signal processing, e.g. mixing of two or more signals · CPC title

• H01J2237/2817

  Pattern inspection · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title