Oversampling CDR which compensates frequency difference without elasticity buffer

Patent metadata

Field	Value
Publication number	US-9705665-B2
Application number	US-201615009696-A
Country	US
Kind code	B2
Filing date	Jan 28, 2016
Priority date	Mar 31, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

First claim

The invention claimed is:

1. A clock and data recovery circuit, comprising:
a data input configured to receive input data from an electronic device;
a clock configured to generate a first clock signal;
a phase locked loop configured to receive the first clock signal and generate a plurality of second clock signals mutually out of phase with each other;
a sampler circuit coupled to the phase locked loop and the data input and configured to generate a plurality of samples based on the input data and the second clock signals;
a frequency divider coupled to the phase locked loop and configured to divide a frequency of the first clock signal by a division ratio; and
a unit interval movement controller coupled to the frequency divider and configured to output to the frequency divider a command to change the division ratio from a base value to a repositioning value when a relative position of a selected center sample has drifted from a selected position of a current input data bit by more than a threshold value,
wherein the frequency divider is configured to change the division ratio back to the base value after one clock cycle at the repositioning value.

2. The clock and data recovery circuit of claim 1 , comprising a register coupled to the sampler circuit and configured to store the samples.

3. The clock and data recovery circuit of claim 2 , comprising a phase tracker coupled to the register and configured to provide new center sample positions.

4. The clock and data recovery circuit of claim 3 wherein the phase tracker is coupled to the unit interval movement controller and configured to provide to the unit interval movement controller an indication of the relative position.

5. The clock and data recovery circuit of claim 1 wherein the repositioning value is equal to the base value minus 1.

6. The clock and data recovery circuit of claim 1 wherein the repositioning value is equal to the base value plus 1.

7. A clock and data recovery circuit, comprising:
input means for receiving input data from an electronic device;
clock means for generating a first clock signal;
phase locked loop means for receiving the first clock signal and generating a plurality of second clock signals mutually out of phase with each other;
sampler means for generating a plurality of samples based on the input data and the second clock signals;
frequency divider means for dividing a frequency of the first clock signal by a division ratio; and
unit interval movement controller means for outputting to the frequency divider means a command to change the division ratio from a base value to a repositioning value when a relative position of a selected center sample has drifted from a selected position of a current input data bit by more than a threshold value,
wherein the frequency divider means changes the division ratio back to the base value after one clock cycle at the repositioning value.

8. The clock and data recovery circuit of claim 7 , comprising storage means for storing the samples.

9. The clock and data recovery circuit of claim 8 , comprising phase tracker means for providing new center sample positions.

10. The clock and data recovery circuit of claim 9 wherein the phase tracker means provides to the unit interval movement controller means an indication of the relative position.

11. The clock and data recovery circuit of claim 7 wherein the repositioning value is equal to the base value minus 1.

12. The clock and data recovery circuit of claim 7 wherein the repositioning value is equal to the base value plus 1.

13. A method, comprising:
receiving input data from an electronic device;
generating a first clock signal;
generating a plurality of second clock signals mutually out of phase with each other;
generating a plurality of samples based on the input data and the second clock signals;
dividing a frequency of the first clock signal by a division ratio;
generating a command to change the division ratio from a base value to a repositioning value when a relative position of a selected center sample has drifted from a selected position of a current input data bit by more than a threshold value; and
changing the division ratio back to the base value after one clock cycle at the repositioning value.

14. The method of claim 13 wherein the repositioning value is equal to the base value minus 1, or the repositioning value is equal to the base value plus 1.

15. The method of claim 14 , comprising generating new center sample positions.

16. The method of claim 15 , comprising generating an indication of the relative position.

Assignees

• St Microelectronics Int Nv

Inventors

• Chowdhary Abhishek
• Uppal Vivek
• Kaushik Alok
• Mandal Sajal Kumar
• Nandy Tapas
• Chopra Sanjeev

Classifications

• H04L7/0338 Primary

  the correction of the phase error being performed by a feed forward loop · CPC title

• H04L7/005

  Correction by an elastic buffer · CPC title

• H04L43/022

  by sampling · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title