Hybrid electro-optically controlled matrix-addressed systems
US-2024322063-A1 · Sep 26, 2024 · US
US9705026B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9705026-B2 |
| Application number | US-201615009271-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 28, 2016 |
| Priority date | Sep 6, 2013 |
| Publication date | Jul 11, 2017 |
| Grant date | Jul 11, 2017 |
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A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.
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What is claimed is: 1. A method of triggering avalanche breakdown in a semiconductor device, the method comprising: providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below and spaced apart from a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer, wherein the electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown at the pn junction in the semiconductor device by absorption of the radiation in the semiconductor device. 2. The method of claim 1 , further comprising electrically coupling the auxiliary semiconductor device and the semiconductor device in parallel. 3. The method of claim 1 , further comprising limiting a current through the auxiliary semiconductor device by electrically connecting at least one of a resistor, a junction field effect transistor, and a depletion mode field effect transistor in series to the auxiliary semiconductor device. 4. The method of claim 1 , further comprising forming the auxiliary semiconductor device and the semiconductor device in a silicon semiconductor body at a distance of less than 50 μm. 5. The method of claim 1 , further comprising adjusting a first breakdown voltage Vbr 1 of a current path through the semiconductor device larger than a second breakdown voltage Vbr 2 of a current path through the auxiliary semiconductor device. 6. The method of claim 1 , further comprising adjusting a first breakdown voltage Vbr 1 of a current path through the semiconductor device equal to or smaller than a second breakdown voltage Vbr 2 of a current path through the auxiliary semiconductor device.
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