Power semiconductor module

Patent metadata

Field	Value
Publication number	US-9704831-B2
Application number	US-201013698901-A
Country	US
Kind code	B2
Filing date	May 21, 2010
Priority date	May 21, 2010
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A transistor chip formed from a wide band gap semiconductor, on which transistor elements for an upper arm are formed is mounted on a front surface of an insulating substrate. A transistor chip formed from a wide band gap semiconductor, on which transistor elements for a lower arm are formed is mounted on a rear surface of the insulating substrate.

First claim

The invention claimed is:

1. A power semiconductor module comprising:
a first insulating substrate, on which conductor patterns are formed;
first transistor elements for a plurality of upper arms mounted on a front surface of the first insulating substrate and formed from a wide band gap semiconductor; and
second transistor elements for a plurality of lower arms mounted on a backside surface of the first insulating substrate which is opposing to the front surface, and formed from a wide band gap semiconductor,
wherein a plurality of phases comprising pairs of the upper arm and the lower arm are connected by inter-phase connection at positive terminals of the upper arms and negative terminals of the lower arms of each of the phases;
wherein the conductor patterns include:
a first direct-current potential side conductor pattern integrally connecting a plurality of pairs of the upper arms for inter-phase connection formed on the front surface of the first insulating substrate; and
a second direct-current potential side conductor pattern integrally connecting a plurality of pairs of the lower arms for inter-phase connection formed on the backside surface of the first insulating substrate and arranged to be opposed to the first direct-current potential side conductor pattern for inter-phase connection to be plane-symmetrical to the first direct-current potential side conductor pattern for inter-phase connection.

2. The power semiconductor module according to claim 1 , further comprising:
a first freewheeling diode element connected to the first transistor element and formed from a wide band gap semiconductor; and
a second freewheeling diode element connected to the second transistor element and formed from a wide band gap semiconductor.

3. The power semiconductor module according to claim 1 , wherein the wide band gap semiconductor is SiC.

4. The power semiconductor module according to claim 1 , wherein the conductor patterns include:
a first direct-current potential side conductor pattern for element arrangement formed on the front surface of the first insulating substrate and connected to the first direct-current potential side conductor pattern for inter-phase connection, the first transistor element being arranged on the first direct-current potential side conductor pattern for element arrangement; and
a second direct-current potential side conductor pattern for element arrangement formed on the backside surface of the first insulating substrate, connected to the second direct-current potential side conductor pattern for inter-phase connection, and arranged to be opposed to the first direct-current potential side conductor pattern for element arrangement to be plane-symmetrical to the first direct-current potential side conductor pattern for element arrangement, the second transistor element being arranged on the second direct-current potential side conductor pattern for chip arrangement.

5. The power semiconductor module according to claim 1 , wherein the first and second direct-current potential side conductor patterns for inter-phase connection are arranged in a peripheral edge portion of the first insulating substrate along a first side of the first insulating substrate.

6. The power semiconductor module according to claim 5 , further comprising a first output conductor pattern arranged for each of phases in the peripheral edge portion of the first insulating substrate along a second side opposed to the first side of the first insulating substrate.

7. The power semiconductor module according to claim 6 , wherein parts of the first output conductor pattern are arranged to be plane-symmetrical to each other on the front surface side and the backside surface side of the first insulating substrate.

8. The power semiconductor module according to claim 7 , wherein the first output conductor pattern is configured to hold the first insulating substrate from above and below by way of a side surface of the first insulating substrate.

9. The power semiconductor module according to claim 1 , wherein direct-current potential surfaces of the first transistor element and the second transistor element are arranged on the first insulating substrate side.

10. The power semiconductor module according to claim 1 , wherein the first direct-current potential side conductor pattern and the second direct-current potential side conductor pattern are separate elements.

11. The power semiconductor module according to claim 1 , wherein the second direct-current potential side conductor pattern is arranged to be vertically aligned via the insulating substrate with the first direct-current potential side conductor pattern.

Assignees

• Hatai Akira
• Tamura Shizuri
• Mitsubishi Electric Corp

Inventors

• Hatai Akira
• Tamura Shizuri

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/657 Primary

  on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title