Semiconductor device and method of forming embedded wafer level chip scale packages

Patent metadata

Field	Value
Publication number	US-9704824-B2
Application number	US-201314070509-A
Country	US
Kind code	B2
Filing date	Nov 2, 2013
Priority date	Jan 3, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (μm) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 μm or less.

First claim

What is claimed:

1. A semiconductor device, comprising:
a semiconductor die including a notch formed in a peripheral region of an active surface of the semiconductor die;
an encapsulant deposited around the semiconductor die and into the notch, wherein a surface of the encapsulant is coplanar with the notched active surface of the semiconductor die; and
a build-up interconnect structure formed over the semiconductor die and entirely within a footprint of the semiconductor die.

2. The semiconductor device of claim 1 , wherein the build-up interconnect structure further includes:
an insulating layer formed over the semiconductor die; and
a conductive layer formed over the insulating layer, the encapsulant devoid of the conductive layer.

3. The semiconductor device of claim 1 , wherein a non-active surface of the semiconductor die is exposed with respect to the encapsulant.

4. The semiconductor device of claim 1 , wherein the encapsulant covers a sidewall of the semiconductor die.

5. The semiconductor device of claim 4 , wherein the encapsulant covering the sidewall of the semiconductor die includes a thickness of 50 micrometers (μm) or less.

Assignees

• Stats Chippac Ltd
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Marimuthu Pandi C
• Shim Il Kwon
• Han Byung Joon

Classifications

• H10P58/00

  Singulating wafers or substrates into multiple chips, i.e. dicing · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title